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面向Duobinary信号的时钟恢复电路研究与设计
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作者 袁梁勇 齐星云 +6 位作者 吕方旭 罗章 黄恒 张庚 王文晨 李萌 赖明澈 《计算机工程与科学》 北大核心 2025年第1期27-34,共8页
高速串行接口是高性能计算机系统中芯片之间的互连核心,针对高速串行通信所需高带宽问题,在Candence平台上基于Verilog-AMS完成56 Gbps Duobinary信号时钟数据恢复电路设计与仿真,多电平传输可以减小对带宽的需求。基于相位差值器(PI)... 高速串行接口是高性能计算机系统中芯片之间的互连核心,针对高速串行通信所需高带宽问题,在Candence平台上基于Verilog-AMS完成56 Gbps Duobinary信号时钟数据恢复电路设计与仿真,多电平传输可以减小对带宽的需求。基于相位差值器(PI)设计时钟数据恢复(CDR)电路,以Bang-Bang鉴相器的鉴相结果作为鉴相依据,采用数字信号处理(DSP)算法处理鉴相结果,其包括投票算法、滤波算法以及相位控制码转换算法。数字算法降低了电路设计的复杂度,便于调节环路增益,提高了系统的稳定性,降低环路延迟。仿真结果表明,该CDR电路可以进行相差和100 PPM频差的追踪。对输入数据分别增加0.25 UI正弦抖动,环路带宽为23 MHz,当抖动频率未超过环路带宽时,系统能够跟踪正弦抖动。抖动容限满足CEI-56G协议规范。 展开更多
关键词 时钟数据恢复 duobinary信号 Bang-Bang鉴相器 数字信号处理算法 正弦抖动
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Multiple-impairment monitoring for optical duobinary system based on delay-tap asynchronous sampling 被引量:1
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作者 赖俊森 杨爱英 孙雨南 《Journal of Beijing Institute of Technology》 EI CAS 2013年第2期246-249,共4页
A technique using artificial neural networks trained with parameters derived from delay tap plots for optical performance monitoring in 40 Gbit/s duobinary system is demonstrated. Firstly, the optical signal is delay ... A technique using artificial neural networks trained with parameters derived from delay tap plots for optical performance monitoring in 40 Gbit/s duobinary system is demonstrated. Firstly, the optical signal is delay tap sampled to obtain two-dimensional histogram, known as delay tap plots. Secondly, the features of delay tap plots are extracted to train the feed forward, three-layer preceptor structure artificial neural networks. Finally, the outputs of trained neural network are used to monitor optical duobinary signal impairments. Simulation of optical signal noise ratio ( OSNR), chromatic dispersion (CD), and differential group delay (DGD) monitoring in 40 Gbit/s optical duo- binary system is presented. The proposed monitoring scheme can accurately identify simultaneous impairments without requiring synchronous sampling or data clock recovery. The proposed technique is simple, cost-effective and suitable for in-service distributed OPM. 展开更多
关键词 optical performance monitoring (OPM) duobinary modulation delay tap sampling
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10Gb/s transmit equalizer using duobinary signaling over FR4 backplane 被引量:1
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作者 张银行 Hu Qingsheng 《High Technology Letters》 EI CAS 2017年第3期266-270,共5页
A 10Gb/s 6-tap transmit equalizer based on partial response signaling for high speed backplane transmission is presented. By combining features of equalizer and frequency-dependent channel,duobinary signaling can be g... A 10Gb/s 6-tap transmit equalizer based on partial response signaling for high speed backplane transmission is presented. By combining features of equalizer and frequency-dependent channel,duobinary signaling can be generated at the output of FR4 backplane,aiming at increasing data rate while reducing design complexity. Based on 0.18μm CMOS technology,this equalizer has been designed and fabricated,in which both variable capacitor and load resistor calibration techniques are explored to eliminate the effect of process variations. The chip occupies 0.68×0.8mm^2 including I/O pads and consumes a power of 194 mW with 1.8V power supply. Measurement results show that a typical 3-level eye diagram can be obtained at the receiver and the equalizer can work properly at the data rate of 10Gb/s. 展开更多
关键词 transmit equalizer duobinary partial response load resistor calibration CMOS technology
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