Dual-output power amplifiers(PAs)have shown great potential in the area of radar,satellite and wireless communication systems.However,the flexibility of the power allocation in a dual-output PA without sacrificing eff...Dual-output power amplifiers(PAs)have shown great potential in the area of radar,satellite and wireless communication systems.However,the flexibility of the power allocation in a dual-output PA without sacrificing efficiency and circuit complexity still needs further investigation.This paper presents a digitally dual-input dual-output(DIDO)PA with reconfigurable modes for power allocation application.The proposed DIDO PA is consist of two identical sub-amplifiers and a 90◦coupler,showing a simple circuit topology.The input amplitudes of the two sub-amplifiers and their phase difference is dynamically controlled leveraging on the dual-input technique,leading to reconfigurable operation modes from power allocation to Doherty.In the power allocation mode,flexible power allocation between two output ports can be obtained by the DIDO PA without sacrificing drain efficiency(DE).On the other hand,flexible power transferring and enhanced back-off DE can be simultaneously achieved by the DIDO PA when it is in the Doherty mode.As a proof of concept,a DIDO PA operating at 2.4 GHz is fabricated and measured in this paper.In the power allocation mode,the DIDO PA achieves a DE of more than 71.8%with a total output power of larger than 44 dBm.Moreover,when the DIDO PA operates in the Doherty mode,it could deliver a maximum output power of more than 44 dBm with a saturation DE of more than 73.9%and a 6 dB back-off DE of more than 61.2%.展开更多
A new current feedback amplifier (CFA) based dual-input differentiator (DID) design with grounded capacitor is presented;its time constant (τo) is independently tunable by a single resistor. The proposed circuit yiel...A new current feedback amplifier (CFA) based dual-input differentiator (DID) design with grounded capacitor is presented;its time constant (τo) is independently tunable by a single resistor. The proposed circuit yields a true DID function with ideal CFA devices. Analysis with nonideal devices having parasitic capacitance (Cp) shows extremely low but finite phase error (θe);suitable design θe could be minimized significantly. The design is practically active-insensitive relative to port mismatch errors (ε) of the active element. An allpass phase shifter circuit implementation is derived with slight modification of the differentiator. Satisfactory experimental results had been verified on typical wave processing and phase-selective filter design applications.展开更多
A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk p...A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.展开更多
The objective of this work is the coordinated design of controllers that can enhance damping of power system swings. With presence of flexible AC transmission system （FACTS） device as unified power flow controller ...The objective of this work is the coordinated design of controllers that can enhance damping of power system swings. With presence of flexible AC transmission system （FACTS） device as unified power flow controller （UPFC）, three specific classes of the power system stabilizers （PSSs） have been investigated. The first one is a conventional power system stabilizer （CPSS）; the second one is a dual-input power system stabilizer （dual-input PSS）; and the third one is an accelerating power PSS model （PSS2B）. Dual-input PSS and PSS2B are introduced to maintain the robustness of control performance in a wide range of swing frequency. Uncoordinated PSS and UPFC damping controller may cause unwanted interactions; therefore, the simultaneous coordinated tuning of the controller parameters is needed. The problem of coordi- nated design is formulated as an optimization problem, and particle swarm optimization （PSO） algorithm is employed to search for optimal parameters of controllers. Finally, in a system having a UPFC, comparative analysis of the results obtained from application of the dual-input PSS, PSS2B, and CPSS is presented. The eigenvalue analysis and the time-domain simulation results show that the dual-input PSS ＆ UPFC and the PSS2B ＆ UPFC coordination provide a better performance than the conventional single-input PSS ＆ UPFC coordination. Also, the PSS2B ＆ UPFC coordination has the best performance.展开更多
基金supported in part by the National Natural Science Foundation of China(No.62201100).
文摘Dual-output power amplifiers(PAs)have shown great potential in the area of radar,satellite and wireless communication systems.However,the flexibility of the power allocation in a dual-output PA without sacrificing efficiency and circuit complexity still needs further investigation.This paper presents a digitally dual-input dual-output(DIDO)PA with reconfigurable modes for power allocation application.The proposed DIDO PA is consist of two identical sub-amplifiers and a 90◦coupler,showing a simple circuit topology.The input amplitudes of the two sub-amplifiers and their phase difference is dynamically controlled leveraging on the dual-input technique,leading to reconfigurable operation modes from power allocation to Doherty.In the power allocation mode,flexible power allocation between two output ports can be obtained by the DIDO PA without sacrificing drain efficiency(DE).On the other hand,flexible power transferring and enhanced back-off DE can be simultaneously achieved by the DIDO PA when it is in the Doherty mode.As a proof of concept,a DIDO PA operating at 2.4 GHz is fabricated and measured in this paper.In the power allocation mode,the DIDO PA achieves a DE of more than 71.8%with a total output power of larger than 44 dBm.Moreover,when the DIDO PA operates in the Doherty mode,it could deliver a maximum output power of more than 44 dBm with a saturation DE of more than 73.9%and a 6 dB back-off DE of more than 61.2%.
文摘A new current feedback amplifier (CFA) based dual-input differentiator (DID) design with grounded capacitor is presented;its time constant (τo) is independently tunable by a single resistor. The proposed circuit yields a true DID function with ideal CFA devices. Analysis with nonideal devices having parasitic capacitance (Cp) shows extremely low but finite phase error (θe);suitable design θe could be minimized significantly. The design is practically active-insensitive relative to port mismatch errors (ε) of the active element. An allpass phase shifter circuit implementation is derived with slight modification of the differentiator. Satisfactory experimental results had been verified on typical wave processing and phase-selective filter design applications.
基金Project supported by the National Natural Science Foundation of China(No.60876019)the National S&T Major Project of China(No. 2009ZX0131-002-003-02)+2 种基金the Shanghai Rising-Star Program(No.09QA1400300)the National Scientists and Engineers Service for Enterprise Program,China(No.2009GJC00046)the ASIC State-Key Laboratory Funding,China(No.09MS007)
文摘A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.
文摘The objective of this work is the coordinated design of controllers that can enhance damping of power system swings. With presence of flexible AC transmission system （FACTS） device as unified power flow controller （UPFC）, three specific classes of the power system stabilizers （PSSs） have been investigated. The first one is a conventional power system stabilizer （CPSS）; the second one is a dual-input power system stabilizer （dual-input PSS）; and the third one is an accelerating power PSS model （PSS2B）. Dual-input PSS and PSS2B are introduced to maintain the robustness of control performance in a wide range of swing frequency. Uncoordinated PSS and UPFC damping controller may cause unwanted interactions; therefore, the simultaneous coordinated tuning of the controller parameters is needed. The problem of coordi- nated design is formulated as an optimization problem, and particle swarm optimization （PSO） algorithm is employed to search for optimal parameters of controllers. Finally, in a system having a UPFC, comparative analysis of the results obtained from application of the dual-input PSS, PSS2B, and CPSS is presented. The eigenvalue analysis and the time-domain simulation results show that the dual-input PSS ＆ UPFC and the PSS2B ＆ UPFC coordination provide a better performance than the conventional single-input PSS ＆ UPFC coordination. Also, the PSS2B ＆ UPFC coordination has the best performance.
