A novel integrated circuit for driving LED lighting has been proposed, designed and fabricated. Besides the typical parts of LED driver, an integral part was added at the output terminal of error amplifier in the driv...A novel integrated circuit for driving LED lighting has been proposed, designed and fabricated. Besides the typical parts of LED driver, an integral part was added at the output terminal of error amplifier in the driver. In this way, a novel average current mode can be set up to take the place ordinary peak current control mode. In addition, a BUCK low-level topology was adopted, too. It can be used to drive up to eight 1 W HB LED lights with 350 mA constant current. In this way, the LED driver displays high performance, in which output current with less 1% error and total efficiency as high as 96%. The feasibility of the design has been verified by actual measurement on the fabricated chip.展开更多
GaN功率器件阈值电压较低且栅极反向击穿电压较小,其应用于高频桥式电路时面临的串扰问题更为严峻。为解决该问题,本文提出一种仅由电阻-电容-二极管(residual current device,RCD)组成,具有正负串扰抑制功能的驱动电路。其基本思路是...GaN功率器件阈值电压较低且栅极反向击穿电压较小,其应用于高频桥式电路时面临的串扰问题更为严峻。为解决该问题,本文提出一种仅由电阻-电容-二极管(residual current device,RCD)组成,具有正负串扰抑制功能的驱动电路。其基本思路是在驱动回路中引入负压电容抑制正向串扰,在驱动电阻两端并联小电阻抑制负向串扰。在分析所提电路工作模态和主要器件参数的基础上,搭建双脉冲和同步Buck实验平台,验证了该电路对正负串扰的抑制能力。实验结果表明,相较于传统驱动电路,在50 V母线电压下,所提驱动电路使器件串扰电压尖峰分别减少3.31 V和1.55 V,同时提高42%的关断速度并降低78.81%的关断损耗。展开更多
A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of...A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation.展开更多
Output-pulse shaping capability of a linear transformer driver （LTD） module under different conditions is studied, by conducting the whole circuit model simulation by using the PSPICE code. Results indicate that a h...Output-pulse shaping capability of a linear transformer driver （LTD） module under different conditions is studied, by conducting the whole circuit model simulation by using the PSPICE code. Results indicate that a higher impedance profile of the internal transmission line would lead to a wider adjustment range for the output current rise time and a narrower adjustment range for the current peak. The number of cavities in series has a positive effect on the output- pulse shaping capability of LTD. Such an improvement in the output-pulse shaping capability can primarily be ascribed to the increment in the axial electric length of LTD. For a triggering time interval longer than the time taken by a pulse to propagate through the length of one cavity, the output parameters of LTD could be improved significantly. The present insulating capability of gas switches and other elements in the LTD cavities may only tolerate a slightly longer deviation in the triggering time interval. It is feasible for the LTD module to reduce the output current rise time, though it is not useful to improve the peak power effectively.展开更多
Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical ...Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.展开更多
A high power buck-boost switch-mode LED driver delivering a constant 350 mA with a power efficient current sensing scheme is presented in this paper. The LED current is extracted by differentiating the output capacito...A high power buck-boost switch-mode LED driver delivering a constant 350 mA with a power efficient current sensing scheme is presented in this paper. The LED current is extracted by differentiating the output capacitor voltage and maintained by a feedback. The circuit has been fabricated in a standard 0.35 μm AMS CMOS process. Measurement results demonstrated a power-conversion efficiency over 90% with a line regulation of 8%/V for input voltage of 3.3 V and current output between 200 mA and 350 mA.展开更多
The recent high-performance interfaces like DDR2, DDR3, USB and Serial ATA require their output drivers to provide a minimum variation of rise and fall times over Process, Voltage, and Temperature (PVT) and output loa...The recent high-performance interfaces like DDR2, DDR3, USB and Serial ATA require their output drivers to provide a minimum variation of rise and fall times over Process, Voltage, and Temperature (PVT) and output load variations. As the interface speed grows up, the output drivers have been important component for high quality signal integrity, because the output voltage levels and slew rate are mainly determined by the output drivers. The output driver impedance compliance with the transmission line is a key factor in noise minimization due to the signal reflections. In this paper, the different implementations of PVT compensation circuits are analyzed for cmos45nm and cmos65nm technology processes. One of the considered PVT compensation circuits uses the analog compensation approach. This circuit was designed in cmos45nm technology. Other two PVT compensation circuits use the digital compensation method. These circuits were designed in cmos65nm technology. Their electrical characteristics are matched with the requirements for I/O drivers with respect to DDR2 and DDR3 standards. DDR2 I/O design was done by the Freescale wireless design team for mobile phones and later was re-used for other high speed interface designs. In conclusion, the advantages and disadvantages of considered PVT control circuits are analyzed.展开更多
This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the ...This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the results of GA, further improving the solution quality. The problem formulation is done in the framework named RUNE (fRamework for aUtomated aNalog dEsign), which targets solving nonlinear mono-objective and multi-objective optimization problems for analog circuits design. Two circuits are presented: a transimpedance amplifier (TIA) and an optical driver (Driver), which are both part of an Optical Network-on-Chip (ONoC). Furthermore, convergence characteristics and robustness of the proposed method have been explored through comparison with results obtained with SQP algorithm. The outcome is very encouraging and suggests that the hybrid proposed method is very efficient in solving analog design problems.展开更多
SiC MOSFET具有低导通电阻、低开关损耗、高开关频率以及优异的反向恢复特性。器件过快的开关速度,会导致严重的开关过冲、振荡和串扰。此外其短路承受能力弱,需要保护电路具备更快的响应速度,但较高的开关变化率,又使得保护电路的快速...SiC MOSFET具有低导通电阻、低开关损耗、高开关频率以及优异的反向恢复特性。器件过快的开关速度,会导致严重的开关过冲、振荡和串扰。此外其短路承受能力弱,需要保护电路具备更快的响应速度,但较高的开关变化率,又使得保护电路的快速响应与抗噪声能力难以兼顾。为确保其安全可靠工作,该文提出基于多段式电平调控的驱动与保护方法。驱动方法解决开关过程多个目标的协同优化问题,在获得较快的开关速度和低损耗的同时,有效地抑制过冲和振荡;保护方法提出了增加补偿回路的导通压降检测电路,降低了温度和负载变化对检测精度的影响,同时提出了两段式降低栅压的关断方法,增大故障检测盲区时间以降低干扰噪声影响,并采用软关断技术,抑制关断过电压。展开更多
文摘A novel integrated circuit for driving LED lighting has been proposed, designed and fabricated. Besides the typical parts of LED driver, an integral part was added at the output terminal of error amplifier in the driver. In this way, a novel average current mode can be set up to take the place ordinary peak current control mode. In addition, a BUCK low-level topology was adopted, too. It can be used to drive up to eight 1 W HB LED lights with 350 mA constant current. In this way, the LED driver displays high performance, in which output current with less 1% error and total efficiency as high as 96%. The feasibility of the design has been verified by actual measurement on the fabricated chip.
基金supported partly by National Natural Science Foundation of China(Nos.50637010,51077111)partly by the State Key Laboratory of Electrical Insulation and Power Equipment of Xi'an Jiaotong University of China(EIPE09207)
文摘A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation.
基金supported by National Natural Science Foundation of China (Nos. 50637010, 51077111)the State Key Laboratory of Electrical Insulation and Power Equipment of Xi'an Jiaotong University of China (EIPE 09207)
文摘Output-pulse shaping capability of a linear transformer driver （LTD） module under different conditions is studied, by conducting the whole circuit model simulation by using the PSPICE code. Results indicate that a higher impedance profile of the internal transmission line would lead to a wider adjustment range for the output current rise time and a narrower adjustment range for the current peak. The number of cavities in series has a positive effect on the output- pulse shaping capability of LTD. Such an improvement in the output-pulse shaping capability can primarily be ascribed to the increment in the axial electric length of LTD. For a triggering time interval longer than the time taken by a pulse to propagate through the length of one cavity, the output parameters of LTD could be improved significantly. The present insulating capability of gas switches and other elements in the LTD cavities may only tolerate a slightly longer deviation in the triggering time interval. It is feasible for the LTD module to reduce the output current rise time, though it is not useful to improve the peak power effectively.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61131001,61322405,61204044,61376039,and 61334003)
文摘Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.
文摘A high power buck-boost switch-mode LED driver delivering a constant 350 mA with a power efficient current sensing scheme is presented in this paper. The LED current is extracted by differentiating the output capacitor voltage and maintained by a feedback. The circuit has been fabricated in a standard 0.35 μm AMS CMOS process. Measurement results demonstrated a power-conversion efficiency over 90% with a line regulation of 8%/V for input voltage of 3.3 V and current output between 200 mA and 350 mA.
文摘The recent high-performance interfaces like DDR2, DDR3, USB and Serial ATA require their output drivers to provide a minimum variation of rise and fall times over Process, Voltage, and Temperature (PVT) and output load variations. As the interface speed grows up, the output drivers have been important component for high quality signal integrity, because the output voltage levels and slew rate are mainly determined by the output drivers. The output driver impedance compliance with the transmission line is a key factor in noise minimization due to the signal reflections. In this paper, the different implementations of PVT compensation circuits are analyzed for cmos45nm and cmos65nm technology processes. One of the considered PVT compensation circuits uses the analog compensation approach. This circuit was designed in cmos45nm technology. Other two PVT compensation circuits use the digital compensation method. These circuits were designed in cmos65nm technology. Their electrical characteristics are matched with the requirements for I/O drivers with respect to DDR2 and DDR3 standards. DDR2 I/O design was done by the Freescale wireless design team for mobile phones and later was re-used for other high speed interface designs. In conclusion, the advantages and disadvantages of considered PVT control circuits are analyzed.
文摘This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the results of GA, further improving the solution quality. The problem formulation is done in the framework named RUNE (fRamework for aUtomated aNalog dEsign), which targets solving nonlinear mono-objective and multi-objective optimization problems for analog circuits design. Two circuits are presented: a transimpedance amplifier (TIA) and an optical driver (Driver), which are both part of an Optical Network-on-Chip (ONoC). Furthermore, convergence characteristics and robustness of the proposed method have been explored through comparison with results obtained with SQP algorithm. The outcome is very encouraging and suggests that the hybrid proposed method is very efficient in solving analog design problems.
