A down-scaled operational oceanographic system is developed for the coastal waters of Korea using a re- gional ocean modeling system （ROMS）. The operational oceanographic modeling system consists of at- mospheric an...A down-scaled operational oceanographic system is developed for the coastal waters of Korea using a re- gional ocean modeling system （ROMS）. The operational oceanographic modeling system consists of at- mospheric and hydrodynamic models. The hydrodynamic model, ROMS, is coupled with wave, sediment transport, and water quality modules. The system forecasts the predicted results twice a day on a 72 h basis, including sea surface elevation, currents, temperature, salinity, storm surge height, and wave information for the coastal waters of Korea. The predicted results are exported to the web-GIS-based coastal informa- tion system for real-time dissemination to the public and validation with real-time monitoring data using visualization technologies. The ROMS is two-way coupled with a simulating waves nearshore model, SWAN, for the hydrodynamics and waves, nested with the meteorological model, WRE for the atmospheric surface forcing, and externally nested with the eutrophication model, CE-QUAL-ICM, for the water quality. The op- erational model, ROMS, was calibrated with the tidal surface observed with a tide-gage and verified with current data observed by bottom-mounted ADCP or AWAC near the coastal waters of Korea. To validate the predicted results, we used real-time monitoring data derived from remote buoy system, HF-radar, and geostationary ocean color imager （GOCI）. This down-scaled operational coastal forecasting system will be used as a part of the Korea operational oceanographic system （KOOS） with other operational oceanographic systems.展开更多
Although the coding modes of H.264 coded video would be changed by the transcoding process of spatial resolution reduction, there exists good correlation in prediction modes and prediction directions between input and...Although the coding modes of H.264 coded video would be changed by the transcoding process of spatial resolution reduction, there exists good correlation in prediction modes and prediction directions between input and output video. In this paper, we first introduce a new spatial resolution reduction transcoding architecture of intra coded frames where the distortion can be calculated directly in compression domain. We then propose a fast mode decision algorithm in which only a small part of rate distortion optimization （RDO） calculation is needed for mode decision. For 4×4 luma block, the proposed scheme has average 21.3% computation saving, compared to the cascaded pixel-domain transcoding scheme with the fast intra mode decision algorithm proposed in JVT-G013. For 16×16 luma block, RDO calculation is completely avoided in our scheme while the scheme in JVT-G013 needs 2 RDO calculations. Experimental results show that our scheme outperforms that of JVT-G013 in terms of significantly computasavings with negligible loss of PSNR展开更多
A low-jitter RF phase locked loop（PLL） frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed.Several techniques are proposed to reduce the design complexity and improve the performance...A low-jitter RF phase locked loop（PLL） frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed.Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL.An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit.Through integrating the D-latch with ＇OR＇ logic for dual-modulus operation,the delays associated with both the ＇OR＇ and D-flip-flop（DFF） operations are reduced,and the complexity of the circuit is also decreased.The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model.The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system.The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process. The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz.The circuit exhibits a low RMS jitter of 3.3 ps.The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply.展开更多
A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are adopted t...A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are adopted to improve its performance. A dual-modulus prescaler （DMP） with low phase noise is realized with a kind of improved source-coupled logic （SCL） D-flip-flop （DFF） in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave （CMOS MS）-DFF in the asynchronous divider. A new more accurate wire-load model is used to realize the pulse-swallow counter （PS counter）. Fabricated in a 0.18-#m CMOS process, the total chip size is 0.6× 0.2 mm2. The DMP in the proposed down-scaling circuit exhibits a low phase noise of-118.2 dBc/Hz at 10 kHz off the carrier frequency. At a supply voltage of 1.8 V, the power consumption of the down-scaling circuit＇s core part is only 2.7 mW.展开更多
基金The project entitled Cooperation on the Development of Basic Technologies for the Yellow Sea and East China Sea Operational Oceanographic System funded by the China-Korea Joint Ocean Research Centerthe project entitled"Development of Korea Operational Oceanographic System"funded by the Ministry of Oceans and Fisheries,Koreathe project Functional Improvement of Korea Ocean Satellite Center and Development of the Marine Environment Impact Prediction Program funded by the Korea Institute of Ocean Science and Technology
文摘A down-scaled operational oceanographic system is developed for the coastal waters of Korea using a re- gional ocean modeling system （ROMS）. The operational oceanographic modeling system consists of at- mospheric and hydrodynamic models. The hydrodynamic model, ROMS, is coupled with wave, sediment transport, and water quality modules. The system forecasts the predicted results twice a day on a 72 h basis, including sea surface elevation, currents, temperature, salinity, storm surge height, and wave information for the coastal waters of Korea. The predicted results are exported to the web-GIS-based coastal informa- tion system for real-time dissemination to the public and validation with real-time monitoring data using visualization technologies. The ROMS is two-way coupled with a simulating waves nearshore model, SWAN, for the hydrodynamics and waves, nested with the meteorological model, WRE for the atmospheric surface forcing, and externally nested with the eutrophication model, CE-QUAL-ICM, for the water quality. The op- erational model, ROMS, was calibrated with the tidal surface observed with a tide-gage and verified with current data observed by bottom-mounted ADCP or AWAC near the coastal waters of Korea. To validate the predicted results, we used real-time monitoring data derived from remote buoy system, HF-radar, and geostationary ocean color imager （GOCI）. This down-scaled operational coastal forecasting system will be used as a part of the Korea operational oceanographic system （KOOS） with other operational oceanographic systems.
文摘Although the coding modes of H.264 coded video would be changed by the transcoding process of spatial resolution reduction, there exists good correlation in prediction modes and prediction directions between input and output video. In this paper, we first introduce a new spatial resolution reduction transcoding architecture of intra coded frames where the distortion can be calculated directly in compression domain. We then propose a fast mode decision algorithm in which only a small part of rate distortion optimization （RDO） calculation is needed for mode decision. For 4×4 luma block, the proposed scheme has average 21.3% computation saving, compared to the cascaded pixel-domain transcoding scheme with the fast intra mode decision algorithm proposed in JVT-G013. For 16×16 luma block, RDO calculation is completely avoided in our scheme while the scheme in JVT-G013 needs 2 RDO calculations. Experimental results show that our scheme outperforms that of JVT-G013 in terms of significantly computasavings with negligible loss of PSNR
基金supported by the Specialized Research Fund for the Doctoral Program of Higher Education,China(No.20090092120012)the National Natural Science Foundation of China(No.60901012)Natural Science Foundation of Jiangsu Province,China (No.BK2009153).
文摘A low-jitter RF phase locked loop（PLL） frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed.Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL.An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit.Through integrating the D-latch with ＇OR＇ logic for dual-modulus operation,the delays associated with both the ＇OR＇ and D-flip-flop（DFF） operations are reduced,and the complexity of the circuit is also decreased.The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model.The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system.The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process. The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz.The circuit exhibits a low RMS jitter of 3.3 ps.The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply.
基金supported by the National Natural Science Foundation of China(No.61106024)the Specialized Research Fund for the Doctoral Program of Higher Education,China(No.20090092120012)the Science and Technology Program of Southeast University(No. KJ2010402)
文摘A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are adopted to improve its performance. A dual-modulus prescaler （DMP） with low phase noise is realized with a kind of improved source-coupled logic （SCL） D-flip-flop （DFF） in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave （CMOS MS）-DFF in the asynchronous divider. A new more accurate wire-load model is used to realize the pulse-swallow counter （PS counter）. Fabricated in a 0.18-#m CMOS process, the total chip size is 0.6× 0.2 mm2. The DMP in the proposed down-scaling circuit exhibits a low phase noise of-118.2 dBc/Hz at 10 kHz off the carrier frequency. At a supply voltage of 1.8 V, the power consumption of the down-scaling circuit＇s core part is only 2.7 mW.
