A direct conversion receiver with optimized tolerance to local carrier interference is designed and implemented in a 0.18μm 1P6M mixed-signal CMOS process for a 900MHz RFID reader transceiver. A baseband amplifier wi...A direct conversion receiver with optimized tolerance to local carrier interference is designed and implemented in a 0.18μm 1P6M mixed-signal CMOS process for a 900MHz RFID reader transceiver. A baseband amplifier with series feedback topology is proposed to achieve passive mixer buffering,baseband DC cancellation,and signal amplification simultaneously. The receiver has a measured input ldB compression point of - 4dBm and a sensitivity of - 70dBm when 10dB SNR for digital demodulation is required. The receiver is integrated in a reader transceiver chip and consumes 90mA from a 1.8V supply.展开更多
An automatic IQ phase calibration method implemented in a 2.4GHz direct conversion receiver is proposed. It uses a delay locked loop （DLL） with a proposed quadrature phase detector to greatly reduce the phase error....An automatic IQ phase calibration method implemented in a 2.4GHz direct conversion receiver is proposed. It uses a delay locked loop （DLL） with a proposed quadrature phase detector to greatly reduce the phase error. The receiver is fabricated in a 0.18μm CMOS process. Measurements show that the IQ phase error can be calibrated within 1°,which satisfies the system requirement.展开更多
This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,th...This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.展开更多
A CMOS variable gain amplifier（VGA） that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver...A CMOS variable gain amplifier（VGA） that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved.The three-stage VGA with automatic gain control（AGC） and DC offset cancellation（DCOC） is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ±1 dB.The 3-dB bandwidth is over 8 MHz at all gain settings.The measured input-referred third intercept point（IIP3） of the proposed VGA varies from-18.1 to 13.5 dBm,and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz.The dynamic range of the closed-loop AGC exceeds 56 dB,where the output signal-to-noise-and-distortion ratio（SNDR） reaches 20 dB.The whole circuit,occupying 0.3 mm^2 of chip area,dissipates less than 3.7 mA from a 1.8-V supply.展开更多
An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 m CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity...An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 m CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 dB and a dynamic range of 10 dB. Measured noise figure is 8.2 dB, an IIP2 of 63 dBm, an IIP3 of 17 dBm at the minimum gain of 30 dB. The downconverter consumes about 7.7 m A under a supply of 1.2 V.展开更多
基金the Science and Technology Commission of Shanghai Municipality(No.057062010)the EU BRIDGE Project(No.033546)~~
文摘A direct conversion receiver with optimized tolerance to local carrier interference is designed and implemented in a 0.18μm 1P6M mixed-signal CMOS process for a 900MHz RFID reader transceiver. A baseband amplifier with series feedback topology is proposed to achieve passive mixer buffering,baseband DC cancellation,and signal amplification simultaneously. The receiver has a measured input ldB compression point of - 4dBm and a sensitivity of - 70dBm when 10dB SNR for digital demodulation is required. The receiver is integrated in a reader transceiver chip and consumes 90mA from a 1.8V supply.
文摘An automatic IQ phase calibration method implemented in a 2.4GHz direct conversion receiver is proposed. It uses a delay locked loop （DLL） with a proposed quadrature phase detector to greatly reduce the phase error. The receiver is fabricated in a 0.18μm CMOS process. Measurements show that the IQ phase error can be calibrated within 1°,which satisfies the system requirement.
文摘This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.
文摘A CMOS variable gain amplifier（VGA） that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved.The three-stage VGA with automatic gain control（AGC） and DC offset cancellation（DCOC） is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ±1 dB.The 3-dB bandwidth is over 8 MHz at all gain settings.The measured input-referred third intercept point（IIP3） of the proposed VGA varies from-18.1 to 13.5 dBm,and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz.The dynamic range of the closed-loop AGC exceeds 56 dB,where the output signal-to-noise-and-distortion ratio（SNDR） reaches 20 dB.The whole circuit,occupying 0.3 mm^2 of chip area,dissipates less than 3.7 mA from a 1.8-V supply.
基金supported by the Science and Technology Innovation Project for the Postgraduates of National University of Defense Technology
文摘An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 m CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 dB and a dynamic range of 10 dB. Measured noise figure is 8.2 dB, an IIP2 of 63 dBm, an IIP3 of 17 dBm at the minimum gain of 30 dB. The downconverter consumes about 7.7 m A under a supply of 1.2 V.
