All-optical analog-to-digital conversion (ADC) has been extensively researched to break through the inherently limited operating speed of electronic devices. In this paper, we use the photonic crystal fiber (PCF) for ...All-optical analog-to-digital conversion (ADC) has been extensively researched to break through the inherently limited operating speed of electronic devices. In this paper, we use the photonic crystal fiber (PCF) for time-stretch (TS) analog-to-digital (A/D) conversion system through generating low noise, linear chirp distribution and flat super-continuum (SC). Based on the radio frequency (RF) analog signal modulated to the linearly chirped super-continuum, the large-dispersion photonic crystal fiber is used for time-domain stretching.展开更多
An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integra...An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift （SSFS） module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/（km.nm） with ＋0.5 ps/（km.nm） variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate （MSSR） is 50.45 GSa/s with full width at half maximum （FWHM） variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.展开更多
We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of pho...We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.展开更多
We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg gratin...We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg grating is optimally designed and used to compensate for the entire time-delays of the quantized pulses precisely. Simulation results show that the compensated coding pulses are well synchronized with a time difference less than 3.3 ps, which can support a maximum sampling rate of 151.52 GSa/s. The proposed scheme can efficiently reduce the structure complexity and cost of all-optical analog-to-digital conversion compared to the previous schemes with multiple optical time-delay lines.展开更多
The application of legal texts in the context of digital television is a process that relies on several normative instruments,ranging from international treaties,such as those of the ITU(International Telecommunicatio...The application of legal texts in the context of digital television is a process that relies on several normative instruments,ranging from international treaties,such as those of the ITU(International Telecommunications Union),to national regulations defining the obligations of audiovisual operators and the modalities of consumer support.Many countries have introduced specific laws and regulations to organize the gradual switch-off of analog broadcasting and encourage the adoption of new digital standards.Consequently,the digitization of Guinea’s broadcasting network cannot be carried out without taking into account the legal framework:allocation of resources and broadcasting players.Analog and digital broadcasting,according to regulatory texts,shows the relationships between the different communication management structures.As for digital broadcasting,we note the appearance of a new service,multiplex.展开更多
A largescale antenna system （LSAS） with digital beamforming is expected to significantly increase energy efficiency （EE） and spectral efficiency （SE） in a wireless communication system. However, there are many c...A largescale antenna system （LSAS） with digital beamforming is expected to significantly increase energy efficiency （EE） and spectral efficiency （SE） in a wireless communication system. However, there are many challenging issues related to calibration, energy consumption, and cost in implementing a digital beamforming structure in an LSAS. In a practical LSAS deployment, hybrid digitalanalog beamforming structures with active antennas can be used. In this paper, we investigate the optimal antenna configuration in an N ＆#215; M beamforming structure, where N is the number of transceivers, M is the number of active antennas per transceiver, where analog beamforming is introduced for individual transceivers and digital beamforming is introduced across all N transceivers. We analyze the green point, which is the point of maximum EE on the EESE curve, and show that the logscale EE scales linearly with SE along a slope of lg2/N. We investigate the effect of M on EE for a given SE value in the case of fixed NM and independent N and M. In both cases, there is a unique optimal M that results in optimal EE. In the case of independent N and M, there is no optimal （N, M） combination for optimizing EE. The results of numerical simulations are provided, and these results support our analysis.展开更多
A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary vol...A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.展开更多
In this paper,we present a novel first-order digitalΣΔconverter tailored for digital-to-analog applications,focusing on achieving both high yield and reduced silicon estate.Our approach incorporates a substantial le...In this paper,we present a novel first-order digitalΣΔconverter tailored for digital-to-analog applications,focusing on achieving both high yield and reduced silicon estate.Our approach incorporates a substantial level of dithering noise into the input signal,strategically aimed at mitigating the spurious frequencies commonly encountered in such converters.Validation of our design is performed through simulations using a high-level simulator specialized in mixed-signal circuit analysis.The results underscore the enhanced performance of our circuit,especially in reducing spurious frequencies,highlighting its efficiency and effectiveness.The final circuit exhibits an effective number of bits of 13.展开更多
This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. A...This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.展开更多
A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC ...A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.展开更多
An electro-absorption(EA)modulator is one of key components for optical fiber communications due to the high speed,small size,low voltage and integration ability with other semiconductor devices.A 40 Gb/s InGaAsP/InP ...An electro-absorption(EA)modulator is one of key components for optical fiber communications due to the high speed,small size,low voltage and integration ability with other semiconductor devices.A 40 Gb/s InGaAsP/InP multiplequantum-well(MQW)EA modulator monolithically integrated with a semiconductor optical amplifier(SOA)was fabricated for digital communications.The modulator capacitance was reduced to obtain 40 GHz bandwidth,and the SOA section helped reduce the insertion loss from 18 dB to 3 dB.InGaAlAs/InP MQW EA modulators have also been fabricated and characterized for analog optical fiber communications.A low driving voltage of 2.7 V and high spurious free dynamic range of 107 dB·Hz2/3 were estimated by static and dynamic measurements.展开更多
The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are inv...The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.展开更多
There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil t...There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.展开更多
A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to e...A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.展开更多
The report examines the evolution of computers from digital analogs through non-yon Neumann machines to quantum computers, which are also digital analogs. In the 60 years of digital analogs successfully developed at t...The report examines the evolution of computers from digital analogs through non-yon Neumann machines to quantum computers, which are also digital analogs. In the 60 years of digital analogs successfully developed at the Institute of Electromechanics of the USSR in Leningrad. An important stage in the development of non-classical multiprocessor machine performance and reliability has been the development of recursive machines, which was carried out at the Institute of Cybernetics led V.M.Glushkov and the Leningrad Institute of Aviation Instrumentation. The general approach to the synthesis is carried out through linguo- combinatorial modeling with structured uncertainty.展开更多
In the field of radiocommunication, modulation type identification is one of the most important characteristics in signal processing. This study aims to implement a modulation recognition system on two approaches to m...In the field of radiocommunication, modulation type identification is one of the most important characteristics in signal processing. This study aims to implement a modulation recognition system on two approaches to machine learning techniques, the K-Nearest Neighbors (KNN) and Artificial Neural Networks (ANN). From a statistical and spectral analysis of signals, nine key differentiation features are extracted and used as input vectors for each trained model. The feature extraction is performed by using the Hilbert transform, the forward and inverse Fourier transforms. The experiments with the AMC Master dataset classify ten (10) types of analog and digital modulations. AM_DSB_FC, AM_DSB_SC, AM_USB, AM_LSB, FM, MPSK, 2PSK, MASK, 2ASK, MQAM are put forward in this article. For the simulation of the chosen model, signals are polluted by the Additive White Gaussian Noise (AWGN). The simulation results show that the best identification rate is the MLP neuronal method with 90.5% of accuracy after 10 dB signal-to-noise ratio value, with a shift of more than 15% from the k-nearest neighbors’ algorithm.展开更多
A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sa...A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.展开更多
Digital circuit and analog circuit courses are basic courses for students of science and engineering universities. Among them,the practical courses are of great significance for students to master the knowledge of ele...Digital circuit and analog circuit courses are basic courses for students of science and engineering universities. Among them,the practical courses are of great significance for students to master the knowledge of electronics. In order to make teachers teaching more efficiently and students studying more quickly,how to update the experimental course in teaching reform is the key point. This paper analyzing the present situation of teaching in the digital circuit and analog circuit courses,the teaching questions in universities. On the basis of it,the innovation measures of experimental teaching methods and contents are discussed. Our school tries to introduce the UltraLab network experiment platform,reform and optimize the teaching methods of related courses.And it’ s accelerating the construction and development of emerging engineering education’ s process,reducing effectively the teacher’s time for managing in equipment,improving the students’ ability to use instruments.展开更多
A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital c...A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.展开更多
With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to co...With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.展开更多
基金supported by the Doctoral Program of Higher Education Research Fund (No.1101.01.001.672)
文摘All-optical analog-to-digital conversion (ADC) has been extensively researched to break through the inherently limited operating speed of electronic devices. In this paper, we use the photonic crystal fiber (PCF) for time-stretch (TS) analog-to-digital (A/D) conversion system through generating low noise, linear chirp distribution and flat super-continuum (SC). Based on the radio frequency (RF) analog signal modulated to the linearly chirped super-continuum, the large-dispersion photonic crystal fiber is used for time-domain stretching.
基金supported by the Fundamental Research Funds for the Central Universities,China(Grant No.FRF-TP-15-030A1)China Postdoctoral Science Foundation(Grant No.2015M580978)
文摘An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift （SSFS） module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/（km.nm） with ＋0.5 ps/（km.nm） variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate （MSSR） is 50.45 GSa/s with full width at half maximum （FWHM） variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.
文摘We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.
基金Project supported by the National Basic Research Program,China(Grant Nos.2010CB327605 and 2010CB328300)the National High-Technology Research and Development Program of China(Grant No.2013AA031501)+7 种基金the National Natural Science Foundation of China(Grant No.61307109)the Specialized Research Fund for the Doctoral Program of Higher Education of China(Grant No.20120005120021)the Fundamental Research Funds for the Central Universities,China(Grant No.2013RC1202)the Program for New Century Excellent Talents in University,China(Grant No.NECT-11-0596)the Beijing Nova Program,China(Grant No.2011066)the Fund of State Key Laboratory of Information Photonics and Optical Communications(Beijing University of Posts and Telecommunications) Chinathe China Postdoctoral Science Foundation(Grant No.2012M511826)the Postdoctoral Science Foundation of Guangdong Province,China(Grant No.244331)
文摘We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg grating is optimally designed and used to compensate for the entire time-delays of the quantized pulses precisely. Simulation results show that the compensated coding pulses are well synchronized with a time difference less than 3.3 ps, which can support a maximum sampling rate of 151.52 GSa/s. The proposed scheme can efficiently reduce the structure complexity and cost of all-optical analog-to-digital conversion compared to the previous schemes with multiple optical time-delay lines.
文摘The application of legal texts in the context of digital television is a process that relies on several normative instruments,ranging from international treaties,such as those of the ITU(International Telecommunications Union),to national regulations defining the obligations of audiovisual operators and the modalities of consumer support.Many countries have introduced specific laws and regulations to organize the gradual switch-off of analog broadcasting and encourage the adoption of new digital standards.Consequently,the digitization of Guinea’s broadcasting network cannot be carried out without taking into account the legal framework:allocation of resources and broadcasting players.Analog and digital broadcasting,according to regulatory texts,shows the relationships between the different communication management structures.As for digital broadcasting,we note the appearance of a new service,multiplex.
文摘A largescale antenna system （LSAS） with digital beamforming is expected to significantly increase energy efficiency （EE） and spectral efficiency （SE） in a wireless communication system. However, there are many challenging issues related to calibration, energy consumption, and cost in implementing a digital beamforming structure in an LSAS. In a practical LSAS deployment, hybrid digitalanalog beamforming structures with active antennas can be used. In this paper, we investigate the optimal antenna configuration in an N ＆#215; M beamforming structure, where N is the number of transceivers, M is the number of active antennas per transceiver, where analog beamforming is introduced for individual transceivers and digital beamforming is introduced across all N transceivers. We analyze the green point, which is the point of maximum EE on the EESE curve, and show that the logscale EE scales linearly with SE along a slope of lg2/N. We investigate the effect of M on EE for a given SE value in the case of fixed NM and independent N and M. In both cases, there is a unique optimal M that results in optimal EE. In the case of independent N and M, there is no optimal （N, M） combination for optimizing EE. The results of numerical simulations are provided, and these results support our analysis.
文摘A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.
文摘In this paper,we present a novel first-order digitalΣΔconverter tailored for digital-to-analog applications,focusing on achieving both high yield and reduced silicon estate.Our approach incorporates a substantial level of dithering noise into the input signal,strategically aimed at mitigating the spurious frequencies commonly encountered in such converters.Validation of our design is performed through simulations using a high-level simulator specialized in mixed-signal circuit analysis.The results underscore the enhanced performance of our circuit,especially in reducing spurious frequencies,highlighting its efficiency and effectiveness.The final circuit exhibits an effective number of bits of 13.
基金supported in part by the National Natural Science Foundation of China under Grant No.61006027the New Century Excellent Talents Program of the Ministry of Education of China under Grant No.NCET-10-0297the Fundamental Research Funds for Central Universities under Grant No.ZYGX2012J003
文摘This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.
文摘A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.
基金supported by National ScienceFoundation Programs(60536020,60723002)"973"State Key Basic Research Programs(2006CB302800,2006CB921106)
文摘An electro-absorption(EA)modulator is one of key components for optical fiber communications due to the high speed,small size,low voltage and integration ability with other semiconductor devices.A 40 Gb/s InGaAsP/InP multiplequantum-well(MQW)EA modulator monolithically integrated with a semiconductor optical amplifier(SOA)was fabricated for digital communications.The modulator capacitance was reduced to obtain 40 GHz bandwidth,and the SOA section helped reduce the insertion loss from 18 dB to 3 dB.InGaAlAs/InP MQW EA modulators have also been fabricated and characterized for analog optical fiber communications.A low driving voltage of 2.7 V and high spurious free dynamic range of 107 dB·Hz2/3 were estimated by static and dynamic measurements.
基金supported by the National Natural Science Foundation of China (Grant No. 11205038)the China Postdoctoral Science Foundation (Grant No. 2012M510951)
文摘The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.
文摘There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.
文摘A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.
文摘The report examines the evolution of computers from digital analogs through non-yon Neumann machines to quantum computers, which are also digital analogs. In the 60 years of digital analogs successfully developed at the Institute of Electromechanics of the USSR in Leningrad. An important stage in the development of non-classical multiprocessor machine performance and reliability has been the development of recursive machines, which was carried out at the Institute of Cybernetics led V.M.Glushkov and the Leningrad Institute of Aviation Instrumentation. The general approach to the synthesis is carried out through linguo- combinatorial modeling with structured uncertainty.
文摘In the field of radiocommunication, modulation type identification is one of the most important characteristics in signal processing. This study aims to implement a modulation recognition system on two approaches to machine learning techniques, the K-Nearest Neighbors (KNN) and Artificial Neural Networks (ANN). From a statistical and spectral analysis of signals, nine key differentiation features are extracted and used as input vectors for each trained model. The feature extraction is performed by using the Hilbert transform, the forward and inverse Fourier transforms. The experiments with the AMC Master dataset classify ten (10) types of analog and digital modulations. AM_DSB_FC, AM_DSB_SC, AM_USB, AM_LSB, FM, MPSK, 2PSK, MASK, 2ASK, MQAM are put forward in this article. For the simulation of the chosen model, signals are polluted by the Additive White Gaussian Noise (AWGN). The simulation results show that the best identification rate is the MLP neuronal method with 90.5% of accuracy after 10 dB signal-to-noise ratio value, with a shift of more than 15% from the k-nearest neighbors’ algorithm.
基金The National Science Fund for Creative Re-search Groups( Grant No 60521002 )Shanghai Natural Science Foundation (GrantNo 037062022)
文摘A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.
基金supported by University-level Teaching Reform Project of New Engineering,Beijing University of Chemical Technology(xgk2017040436)Teaching Reform Project of School of International Teaching,Beijing University of Chemical Technology(siejg201713)
文摘Digital circuit and analog circuit courses are basic courses for students of science and engineering universities. Among them,the practical courses are of great significance for students to master the knowledge of electronics. In order to make teachers teaching more efficiently and students studying more quickly,how to update the experimental course in teaching reform is the key point. This paper analyzing the present situation of teaching in the digital circuit and analog circuit courses,the teaching questions in universities. On the basis of it,the innovation measures of experimental teaching methods and contents are discussed. Our school tries to introduce the UltraLab network experiment platform,reform and optimize the teaching methods of related courses.And it’ s accelerating the construction and development of emerging engineering education’ s process,reducing effectively the teacher’s time for managing in equipment,improving the students’ ability to use instruments.
文摘A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.
文摘With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.
