Based on the study of noise performance in CMOS digital pixel sensor （DPS）, a mathematical model of noise is established with the pulse-width-modulation （PWM） principle. Compared with traditional CMOS image sensor...Based on the study of noise performance in CMOS digital pixel sensor （DPS）, a mathematical model of noise is established with the pulse-width-modulation （PWM） principle. Compared with traditional CMOS image sensors, the integration time is different and A/D conversion is implemented in each PWM DPS pixel. Then, the quantitative calculating formula of system noise is derived. It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model, photodiode shot noise does not vary with luminance, but dark current shot noise does. According to increasing photodiode capacitance and the comparator＇s reference voltage or optimizing the mismatch in the comparator, the total noise can be reduced. These results serve as a guideline for the design of PWM DPS.展开更多
The event-based vision sensor(EVS),which can generate efficient spiking data streams by exclusively detecting motion,exemplifies neuromorphic vision methodologies.Generally,its inherent lack of texture features limits...The event-based vision sensor(EVS),which can generate efficient spiking data streams by exclusively detecting motion,exemplifies neuromorphic vision methodologies.Generally,its inherent lack of texture features limits effectiveness in complex vision processing tasks,necessitating supplementary visual information.However,to date,no event-based hybrid vision solution has been developed that preserves the characteristics of complete spike data streams to support synchronous computation architectures based on spiking neural network(SNN).In this paper,we present a novel spike-based sensor with digitized pixels,which integrates the event detection structure with the pulse frequency modulation(PFM)circuit.This design enables the simultaneous output of spiking data that encodes both temporal changes and texture information.Fabricated in 180 nm process,the proposed sensor achieves a resolution of 128×128,a maximum event rate of 960 Meps,a grayscale frame rate of 117.1 kfps,and a measured power consumption of 60.1 mW,which is suited for high-speed,low-latency,edge SNNbased vision computing systems.展开更多
A smart image sensor was developed which integrates a digital pixel image sensor array with an image processor, designed for wireless endoscope capsules. The camera-on-a-chip architecture and its on-chip functionality...A smart image sensor was developed which integrates a digital pixel image sensor array with an image processor, designed for wireless endoscope capsules. The camera-on-a-chip architecture and its on-chip functionality facilitate the design of the packaging and power consumption of the integrated capsule. The power reduction techniques were carried out at both the architectural and circuit level. Gray coding and power gating in the sensor array to eliminate almost 50% of the switch activity on the data bus and more than 99% of the power dissipation in each pixel at a transmitting rate of 2 frames per second. Filtering and compression in the processor reduces the data transmission by more than 2/3. A parallel fully pipelined architecture with a dedicated clock management scheme was implemented in the JPEG-LS engine to reduce the power consumption by 15.7%. The smart sensor has been implemented in 0.18 μm CMOS technology.展开更多
基金supported by the National Natural Science Foundation of China(Nos.60976030,61036004)
文摘Based on the study of noise performance in CMOS digital pixel sensor （DPS）, a mathematical model of noise is established with the pulse-width-modulation （PWM） principle. Compared with traditional CMOS image sensors, the integration time is different and A/D conversion is implemented in each PWM DPS pixel. Then, the quantitative calculating formula of system noise is derived. It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model, photodiode shot noise does not vary with luminance, but dark current shot noise does. According to increasing photodiode capacitance and the comparator＇s reference voltage or optimizing the mismatch in the comparator, the total noise can be reduced. These results serve as a guideline for the design of PWM DPS.
基金supported in part by the National Key Research and Development Program of China(Grant No.2022YFB2804401)the National Natural Science Foundation of China(Grant Nos.62334008,62134004,62404218)+1 种基金the Beijing Natural Science Foundation(Grant No.Z220005)Chinese Academy of Sciences(Grant No.ZDBS-LY-JSC008).
文摘The event-based vision sensor(EVS),which can generate efficient spiking data streams by exclusively detecting motion,exemplifies neuromorphic vision methodologies.Generally,its inherent lack of texture features limits effectiveness in complex vision processing tasks,necessitating supplementary visual information.However,to date,no event-based hybrid vision solution has been developed that preserves the characteristics of complete spike data streams to support synchronous computation architectures based on spiking neural network(SNN).In this paper,we present a novel spike-based sensor with digitized pixels,which integrates the event detection structure with the pulse frequency modulation(PFM)circuit.This design enables the simultaneous output of spiking data that encodes both temporal changes and texture information.Fabricated in 180 nm process,the proposed sensor achieves a resolution of 128×128,a maximum event rate of 960 Meps,a grayscale frame rate of 117.1 kfps,and a measured power consumption of 60.1 mW,which is suited for high-speed,low-latency,edge SNNbased vision computing systems.
文摘A smart image sensor was developed which integrates a digital pixel image sensor array with an image processor, designed for wireless endoscope capsules. The camera-on-a-chip architecture and its on-chip functionality facilitate the design of the packaging and power consumption of the integrated capsule. The power reduction techniques were carried out at both the architectural and circuit level. Gray coding and power gating in the sensor array to eliminate almost 50% of the switch activity on the data bus and more than 99% of the power dissipation in each pixel at a transmitting rate of 2 frames per second. Filtering and compression in the processor reduces the data transmission by more than 2/3. A parallel fully pipelined architecture with a dedicated clock management scheme was implemented in the JPEG-LS engine to reduce the power consumption by 15.7%. The smart sensor has been implemented in 0.18 μm CMOS technology.
