A method of implementing high cost-effective and highly integrated digital lock-in amplifier with microcontroller is discussed. And the digital lock-in amplifier is more suitable for meastwing lowfrequency weak signal...A method of implementing high cost-effective and highly integrated digital lock-in amplifier with microcontroller is discussed. And the digital lock-in amplifier is more suitable for meastwing lowfrequency weak signal. Digital signal sequence is obtained through sampling signal measured over an integer number of signal periods, but digital reference sequence is acquired through mathematical operation, then digital phase sensitive detection can be implemented by calculating the cross-correlation function of digital signal sequence and digital reference sequence. In addition, the frequency response and phase character of the digital lock-in amplifier is analyzed. Finally, the designed digital lock-in amplifier is achieved. Expermental results show that the digital lock-in amplifier can be used for measuring weak signal with low ignal-to-noise ratio.展开更多
In the novel prototype of micro-gyroscope structure,the new configured capacitance sensing scheme for the micro gyroscope was analyzed and the virtual instrument based detection scheme was implemented.The digital lock...In the novel prototype of micro-gyroscope structure,the new configured capacitance sensing scheme for the micro gyroscope was analyzed and the virtual instrument based detection scheme was implemented.The digital lock-in amplifier was employed in the capacitance detection to restrain the noise interference.The capacitance analysis shows that 1 fF capacitance variation corresponds to 0.1 degree of the turn angle.The differential capacitance bridge and the charge integral amplifier were used as the front signal input interface.In the implementation of digital lock-in amplifier,a new routine which warranted the exactly matching of the reference phase to signal phase was proposed.The result of the experiment shows that digital lock-in amplifier can greatly eliminate the noise in the output signal.The non linearity of the turn angle output is 2.3% and the minimum resolution of turn angle is 0.04 degrees.The application of the software demodulation in the signal detection of micro-electro-mechanical-system(MEMS)device is a new attempt,and it shows the prospective for a high-performance application.展开更多
This paper proposes a combination technique of the frequency-domain random demodulation（FRD） and the broadband digital predistorter（DPD）. This technique can linearize the power amplifiers（PAs） at a low sampling ...This paper proposes a combination technique of the frequency-domain random demodulation（FRD） and the broadband digital predistorter（DPD）. This technique can linearize the power amplifiers（PAs） at a low sampling rate in the feedback loop. Based on the theory of compressed sensing（CS）, the FRD method preprocesses the original signal using the frequency domain sampling signal with different stages through multiple parallel channels. Then the FRD method is applied to the broadband DPD system to restrict the sampling process in the feedback loop. The proposed technique is assessed using a 30 W Class-F wideband PA driven by a 20 MHz orthogonal frequency division multiplexing（OFDM） signal, and a 40 W Ga N Doherty PA driven by a 40 MHz 4-carrier long-term evolution（LTE） signal. The simulation and experimental results show that good linearization performance can be achieved at a lower sampling rate with about- 24 d Bc adjacent channel power ratio（ACPR） improvement by applying the proposed combination technique FRD-DPD. Furthermore, the performance of normalized mean square error（NMSE） and error vector magnitude（EVM） also has been much improved compared with the conventional technique.展开更多
This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacit...This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio（SNDR） and an 87.5 dB spurious-free dynamic range（SFDR） with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied.展开更多
文摘A method of implementing high cost-effective and highly integrated digital lock-in amplifier with microcontroller is discussed. And the digital lock-in amplifier is more suitable for meastwing lowfrequency weak signal. Digital signal sequence is obtained through sampling signal measured over an integer number of signal periods, but digital reference sequence is acquired through mathematical operation, then digital phase sensitive detection can be implemented by calculating the cross-correlation function of digital signal sequence and digital reference sequence. In addition, the frequency response and phase character of the digital lock-in amplifier is analyzed. Finally, the designed digital lock-in amplifier is achieved. Expermental results show that the digital lock-in amplifier can be used for measuring weak signal with low ignal-to-noise ratio.
基金The National Natural Science Foundation ofChina(No.60402003)The National High Technology Research and Development Pro-gram of China(863Program)(No.2002AA745120)
文摘In the novel prototype of micro-gyroscope structure,the new configured capacitance sensing scheme for the micro gyroscope was analyzed and the virtual instrument based detection scheme was implemented.The digital lock-in amplifier was employed in the capacitance detection to restrain the noise interference.The capacitance analysis shows that 1 fF capacitance variation corresponds to 0.1 degree of the turn angle.The differential capacitance bridge and the charge integral amplifier were used as the front signal input interface.In the implementation of digital lock-in amplifier,a new routine which warranted the exactly matching of the reference phase to signal phase was proposed.The result of the experiment shows that digital lock-in amplifier can greatly eliminate the noise in the output signal.The non linearity of the turn angle output is 2.3% and the minimum resolution of turn angle is 0.04 degrees.The application of the software demodulation in the signal detection of micro-electro-mechanical-system(MEMS)device is a new attempt,and it shows the prospective for a high-performance application.
基金supported by the National Basic Research Program of China (2014CB339900)the National Hi-Tech Research and Development Program of China (2015AA016801)the National Natural Science Foundation of China (61327806)
文摘This paper proposes a combination technique of the frequency-domain random demodulation（FRD） and the broadband digital predistorter（DPD）. This technique can linearize the power amplifiers（PAs） at a low sampling rate in the feedback loop. Based on the theory of compressed sensing（CS）, the FRD method preprocesses the original signal using the frequency domain sampling signal with different stages through multiple parallel channels. Then the FRD method is applied to the broadband DPD system to restrict the sampling process in the feedback loop. The proposed technique is assessed using a 30 W Class-F wideband PA driven by a 20 MHz orthogonal frequency division multiplexing（OFDM） signal, and a 40 W Ga N Doherty PA driven by a 40 MHz 4-carrier long-term evolution（LTE） signal. The simulation and experimental results show that good linearization performance can be achieved at a lower sampling rate with about- 24 d Bc adjacent channel power ratio（ACPR） improvement by applying the proposed combination technique FRD-DPD. Furthermore, the performance of normalized mean square error（NMSE） and error vector magnitude（EVM） also has been much improved compared with the conventional technique.
基金supported by the Integrated Circuits Program from Shanghai Science and Technology Committee(No.11511505000)
文摘This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio（SNDR） and an 87.5 dB spurious-free dynamic range（SFDR） with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied.
