The infinite time-evolving block decimation algorithm(i TEBD)provides an efficient way to determine the ground state and dynamics of the quantum lattice systems in the thermodynamic limit.In this paper we suggest an o...The infinite time-evolving block decimation algorithm(i TEBD)provides an efficient way to determine the ground state and dynamics of the quantum lattice systems in the thermodynamic limit.In this paper we suggest an optimized way to take the i TEBD calculation,which takes advantage of additional reduced decompositions to speed up the calculation.The numerical calculations show that for a comparable computation time our method provides more accurate results than the traditional i TEBD,especially for lattice systems with large on-site degrees of freedom.展开更多
Integrated sensing and communication(ISAC)is one of the main usage scenarios for 6G wireless networks.To most efficiently utilize the limited wireless resources,integrated super-resolution sensing and communication(IS...Integrated sensing and communication(ISAC)is one of the main usage scenarios for 6G wireless networks.To most efficiently utilize the limited wireless resources,integrated super-resolution sensing and communication(ISSAC)has been recently proposed to significantly improve sensing performance with super-resolution algorithms for ISAC systems,such as the Multiple Signal Classification(MUSIC)algorithm.However,traditional super-resolution sensing algorithms suffer from prohibitive computational complexity of orthogonal-frequency division multiplexing(OFDM)systems due to the large dimensions of the signals in the subcarrier and symbol domains.To address such issues,we propose a novel two-stage approach to reduce the computational complexity for super-resolution range estimation significantly.The key idea of the proposed scheme is to first uniformly decimate signals in the subcarrier domain so that the computational complexity is significantly reduced without missing any target in the range domain.However,the decimation operation may result in range ambiguity due to pseudo peaks,which is addressed by the second stage where the total collocated subcarrier data are used to verify the detected peaks.Compared with traditional MUSIC algorithms,the proposed scheme reduces computational complexity by two orders of magnitude,while maintaining the range resolution and unambiguity.Simulation results verify the effectiveness of the proposed scheme.展开更多
This paper deals with the technology of using comb filters for FIR Decimation in Digital Signal Processing. The process of decreasing the sampling frequency of a sampled signal is called decimation. In the usage of de...This paper deals with the technology of using comb filters for FIR Decimation in Digital Signal Processing. The process of decreasing the sampling frequency of a sampled signal is called decimation. In the usage of decimating filters, only a portion of the out-of-pass band frequencies turns into the pass band, in systems wherein different parts operate at different sample rates. A filter design, tuned to the aliasing frequencies all of which can otherwise steal into the pass band, not only provides multiple stop bands but also exhibits computational efficiency and performance superiority over the single stop band design. These filters are referred to as multiband designs in the family of FIR filters. The other two special versions of FIR filter designs are Halfband and Comb filter designs, both of which are particularly useful for reducing the computational requirements in multirate designs. The proposed method of using Comb FIR decimation procedure is not only efficient but also opens up a new vista of simplicity and elegancy to compute Multiplications per Second (MPS) and Additions per Second (APS) for the desired filter over and above the half band designs.展开更多
Digital down converter （DDC） is the main part of the next generation high frequency （HF） radar. In order to realize the single chip integrations of digital receiver hardware in the next generation HF Radar, a new ...Digital down converter （DDC） is the main part of the next generation high frequency （HF） radar. In order to realize the single chip integrations of digital receiver hardware in the next generation HF Radar, a new design for DDC by using FPGA is presented. Some important and practical applications are given in this paper, and the result can prove the validity. Because we can adjust the parameters freely according to our need, the DDC system can be adapted to the next generation HF radar system.展开更多
基金Project supported by Fundamental Research Funds for the Central Universities(Grant No.FRF-TP-19-013A3)。
文摘The infinite time-evolving block decimation algorithm(i TEBD)provides an efficient way to determine the ground state and dynamics of the quantum lattice systems in the thermodynamic limit.In this paper we suggest an optimized way to take the i TEBD calculation,which takes advantage of additional reduced decompositions to speed up the calculation.The numerical calculations show that for a comparable computation time our method provides more accurate results than the traditional i TEBD,especially for lattice systems with large on-site degrees of freedom.
基金supported by the National Natural Science Foundation of China under Grant No.62071114.
文摘Integrated sensing and communication(ISAC)is one of the main usage scenarios for 6G wireless networks.To most efficiently utilize the limited wireless resources,integrated super-resolution sensing and communication(ISSAC)has been recently proposed to significantly improve sensing performance with super-resolution algorithms for ISAC systems,such as the Multiple Signal Classification(MUSIC)algorithm.However,traditional super-resolution sensing algorithms suffer from prohibitive computational complexity of orthogonal-frequency division multiplexing(OFDM)systems due to the large dimensions of the signals in the subcarrier and symbol domains.To address such issues,we propose a novel two-stage approach to reduce the computational complexity for super-resolution range estimation significantly.The key idea of the proposed scheme is to first uniformly decimate signals in the subcarrier domain so that the computational complexity is significantly reduced without missing any target in the range domain.However,the decimation operation may result in range ambiguity due to pseudo peaks,which is addressed by the second stage where the total collocated subcarrier data are used to verify the detected peaks.Compared with traditional MUSIC algorithms,the proposed scheme reduces computational complexity by two orders of magnitude,while maintaining the range resolution and unambiguity.Simulation results verify the effectiveness of the proposed scheme.
文摘This paper deals with the technology of using comb filters for FIR Decimation in Digital Signal Processing. The process of decreasing the sampling frequency of a sampled signal is called decimation. In the usage of decimating filters, only a portion of the out-of-pass band frequencies turns into the pass band, in systems wherein different parts operate at different sample rates. A filter design, tuned to the aliasing frequencies all of which can otherwise steal into the pass band, not only provides multiple stop bands but also exhibits computational efficiency and performance superiority over the single stop band design. These filters are referred to as multiband designs in the family of FIR filters. The other two special versions of FIR filter designs are Halfband and Comb filter designs, both of which are particularly useful for reducing the computational requirements in multirate designs. The proposed method of using Comb FIR decimation procedure is not only efficient but also opens up a new vista of simplicity and elegancy to compute Multiplications per Second (MPS) and Additions per Second (APS) for the desired filter over and above the half band designs.
文摘Digital down converter （DDC） is the main part of the next generation high frequency （HF） radar. In order to realize the single chip integrations of digital receiver hardware in the next generation HF Radar, a new design for DDC by using FPGA is presented. Some important and practical applications are given in this paper, and the result can prove the validity. Because we can adjust the parameters freely according to our need, the DDC system can be adapted to the next generation HF radar system.
