The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for th...The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.37 mm2.展开更多
This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure i...This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL ≤60.25 LSB, INL ≤6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm^2 in a 1P-8M 55 nm CMOS process.展开更多
A high-speed SiGe BiCMOS direct digital frequency synthesizer（DDS）is presented.The design integrates a high-speed digital DDS core,a high-speed differential current-steering mode 10-bit D/A converter,a serial/parall...A high-speed SiGe BiCMOS direct digital frequency synthesizer（DDS）is presented.The design integrates a high-speed digital DDS core,a high-speed differential current-steering mode 10-bit D/A converter,a serial/parallel interface,and clock control logic.The DDS design is processed in 0.35μm SiGe BiCMOS standard process technology and worked at 1 GHz system frequency.The measured results show that the DDS is capable of generating a frequency-agile analog output sine wave up to 400＋MHz.展开更多
A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in na...A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm^2.展开更多
The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double...The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.展开更多
设计了一个基于金属氧化物薄膜晶体管工艺的8位电流舵数/模转换器(Digital to Analog Converter,DAC),包括定时刷新模块、同步寄存器电路、分段译码电路、开关驱动电路、开关阵列和电流源阵列、多路选择器网络、随机序列发生器。在数字...设计了一个基于金属氧化物薄膜晶体管工艺的8位电流舵数/模转换器(Digital to Analog Converter,DAC),包括定时刷新模块、同步寄存器电路、分段译码电路、开关驱动电路、开关阵列和电流源阵列、多路选择器网络、随机序列发生器。在数字电路中设计定时刷新结构解决了传统的自举逻辑门电荷泄露导致的电流源开关驱动电压的下降,避免了在低频信号下采样出错问题的发生。提出采用差分对偶译码的结构,保证打开和关闭两路信号可以同时到达开关驱动电路,保证驱动电路中电压上升和下降窗口的对称性,减小输出的毛刺;同时利用数字电路中的D触发器和译码电路中的逻辑门实现驱动增强电路,保证可以驱动模拟电路中的高位单位电流源,提高转换速率;利用动态元件匹配(Dynamic Elements Matching,DEM)技术提高DAC的动态性能。后仿真结果表明,所设计的DAC面积为73 mm 2,功耗为6.5 mW,输出电流摆幅为301.46μA,最大转换速率为32 kS/s,在单位电流源的随机匹配误差的标准差为0.1的条件下,奈奎斯特频率下的无杂散动态范围(Spurious-Free Dynamic Range,SFDR)可达到42.43 dB,最大的微分非线性(Differential Nonlinearity,DNL)为0.36 LSB,最大的积分非线性(Integral Nonlinearity,INL)为1.75 LSB,满足生物医学用柔性电子系统的需求。展开更多
This paper addresses the verification of strong currentstate opacity with respect to real-time observations generated from a discrete-event system that is modeled with time labeled Petri nets. The standard current-sta...This paper addresses the verification of strong currentstate opacity with respect to real-time observations generated from a discrete-event system that is modeled with time labeled Petri nets. The standard current-state opacity cannot completely characterize higher-level security. To ensure the higher-level security requirements of a time-dependent system, we propose a strong version of opacity known as strong current-state opacity. For any path(state-event sequence with time information)π derived from a real-time observation that ends at a secret state, the strong current-state opacity of the real-time observation signifies that there is a non-secret path with the same real-time observation as π. We propose general and non-secret state class graphs, which characterize the general and non-secret states of time-dependent systems, respectively. To capture the observable behavior of non-secret states, a non-secret observer is proposed.Finally, we develop a structure called a real-time concurrent verifier to verify the strong current-state opacity of time labeled Petri nets. This approach is efficient since the real-time concurrent verifier can be constructed by solving a certain number of linear programming problems.展开更多
文摘The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.37 mm2.
基金supported by the Major National Science&Technology Program of China(No.2012ZX03004004-002)
文摘This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL ≤60.25 LSB, INL ≤6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm^2 in a 1P-8M 55 nm CMOS process.
基金supported by the National Natural Science Foundation of China(Nos.60773025,60906009)the Program for Changjiang Scholars and Innovative Research Team in University
文摘A high-speed SiGe BiCMOS direct digital frequency synthesizer（DDS）is presented.The design integrates a high-speed digital DDS core,a high-speed differential current-steering mode 10-bit D/A converter,a serial/parallel interface,and clock control logic.The DDS design is processed in 0.35μm SiGe BiCMOS standard process technology and worked at 1 GHz system frequency.The measured results show that the DDS is capable of generating a frequency-agile analog output sine wave up to 400＋MHz.
文摘A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm^2.
文摘The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.
文摘设计了一个基于金属氧化物薄膜晶体管工艺的8位电流舵数/模转换器(Digital to Analog Converter,DAC),包括定时刷新模块、同步寄存器电路、分段译码电路、开关驱动电路、开关阵列和电流源阵列、多路选择器网络、随机序列发生器。在数字电路中设计定时刷新结构解决了传统的自举逻辑门电荷泄露导致的电流源开关驱动电压的下降,避免了在低频信号下采样出错问题的发生。提出采用差分对偶译码的结构,保证打开和关闭两路信号可以同时到达开关驱动电路,保证驱动电路中电压上升和下降窗口的对称性,减小输出的毛刺;同时利用数字电路中的D触发器和译码电路中的逻辑门实现驱动增强电路,保证可以驱动模拟电路中的高位单位电流源,提高转换速率;利用动态元件匹配(Dynamic Elements Matching,DEM)技术提高DAC的动态性能。后仿真结果表明,所设计的DAC面积为73 mm 2,功耗为6.5 mW,输出电流摆幅为301.46μA,最大转换速率为32 kS/s,在单位电流源的随机匹配误差的标准差为0.1的条件下,奈奎斯特频率下的无杂散动态范围(Spurious-Free Dynamic Range,SFDR)可达到42.43 dB,最大的微分非线性(Differential Nonlinearity,DNL)为0.36 LSB,最大的积分非线性(Integral Nonlinearity,INL)为1.75 LSB,满足生物医学用柔性电子系统的需求。
基金supported by the Special Fund for Scientific and Technological Innovation Strategy of Guangdong Province(2022A0505030025)the Science and Technology Fund,FDCT,Macao SAR(0064/2021/A2)
文摘This paper addresses the verification of strong currentstate opacity with respect to real-time observations generated from a discrete-event system that is modeled with time labeled Petri nets. The standard current-state opacity cannot completely characterize higher-level security. To ensure the higher-level security requirements of a time-dependent system, we propose a strong version of opacity known as strong current-state opacity. For any path(state-event sequence with time information)π derived from a real-time observation that ends at a secret state, the strong current-state opacity of the real-time observation signifies that there is a non-secret path with the same real-time observation as π. We propose general and non-secret state class graphs, which characterize the general and non-secret states of time-dependent systems, respectively. To capture the observable behavior of non-secret states, a non-secret observer is proposed.Finally, we develop a structure called a real-time concurrent verifier to verify the strong current-state opacity of time labeled Petri nets. This approach is efficient since the real-time concurrent verifier can be constructed by solving a certain number of linear programming problems.
