By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is su...By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.展开更多
By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric...By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.展开更多
This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for tes...This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set;this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.展开更多
This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure t...This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure to reduce the intersymbolinterference （ISI） of the communication chan nel. By employing inductive peaking technique for the highfrequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decisionfeedback equalizer optimizes the size of the CMLbased circuit such as D flipflops （DFF） and multiplex （MUX）, shortening the feedback path delay and speeding up the operation considerably. Designed in the 0. 181μm CMOS technology, the equalizer delivers 10Gb/s data over 18in FR4 trace with 28dB loss while drawing 27mW from a 1.8V supply. The overall chip area including pads is 0. 6 -0.7mm2.展开更多
This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer （FFE） and a two-tap half-rate de...This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer （FFE） and a two-tap half-rate decision feedback equalizer （DFE） in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm^2.展开更多
The performance of complementary metal oxide semiconductor(CMOS)circuits is affected by electromagnetic interference(EMI),and the study of the circuit's ability to resist EMI will facilitate the design of circuits...The performance of complementary metal oxide semiconductor(CMOS)circuits is affected by electromagnetic interference(EMI),and the study of the circuit's ability to resist EMI will facilitate the design of circuits with better performance.Current-mode CMOS circuits have been continuously developed in recent years due to their advantages of high speed and low power consumption over conventional circuits under the deep submicron process;their EMI resistance performance deserves further study.This paper introduces three kinds of NOT gate circuits:conventional voltage-mode CMOS,MOS current-mode logic(MCML)with voltage signal of input and output,and current-mode CMOS with current signal of input and output.The effects of EMI on three NOT gate circuits are investigated using Cadence Virtuoso software simulation,and a disturbance level factor is defined to compare the effects of different interference terminals,interference signals'waveforms,and interference signals'frequencies on the circuits in the 65 nm process.The relationship between input resistance and circuit EMI resistance performance is investigated by varying the value of cascade resistance at the input of the current-mode CMOS circuits.Simulation results show that the current-mode CMOS circuits have better resistance performance to EMI at high operating frequencies,and the higher the operating frequency of the current-mode CMOS circuits,the better the resistance performance of the circuits to EMI.Additionally,the effects of different temperatures and different processes on the resistance performance of three circuits are also studied.In the temperature range of-40℃to 125℃,the higher the temperature,the weaker the resistance ability of voltage-mode CMOS and MCML circuits,and the stronger the resistance ability of current-mode CMOS circuits.In the 28 nm process,the current-mode CMOS circuit interference resistance ability is relatively stronger than that of the other two kinds of circuits.The relative interference resistance ability of voltage-mode CMOS and MCML circuits in the 28 nm process is similar to that of the 65 nm process,while the relative interference resistance ability of current-mode CMOS circuits in the 28 nm process is stronger than that of the 65 nm process.This study provides a basis for the design of current-mode CMOS circuits against EMI.展开更多
A 37 GHz wide-band programmable divide-by-N frequency divider(FD) composed of a divide-by-2 divider(acting as the first stage) and a divider with a division ratio range of 273–330(acting as the second stage) has been...A 37 GHz wide-band programmable divide-by-N frequency divider(FD) composed of a divide-by-2 divider(acting as the first stage) and a divider with a division ratio range of 273–330(acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider(with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic(DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as-20 d Bm at 32 GHz and the phase noise at 37 GHz is less than-130 d Bc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 m W at a supply voltage of 1.2 V and occupies an area of only 730 μm×475 μm.展开更多
基金Supported by National Natural Science Foundation of China
文摘By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.
基金National Natural Science Foundation of ChinaNatural science Foundation of Zhejiang Province
文摘By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.
文摘This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set;this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.
文摘光纤通信在大数据时代得到广泛的应用,其速度快、带宽大、可靠性高的特点满足了对长距离、大容量信息传输的要求。前置放大器作为光接收器的前端,其性能高低直接影响到整个光接收系统的工作性能。基于SMIC 0.13μm CMOS工艺,设计完成了一款5 Gbps光接收前置放大器。首先,整体差分式结构可以消除共模噪声的干扰,降低放大器的等效输入噪声。其次,采用共源共栅的输入结构具有低输入阻抗的特点,能有效抑制光电管大电容带来的不利影响。最后,输出级采用电流模逻辑结构,解决了输出增益与带宽之间的矛盾。仿真结果表明,放大器增益达到62 d BΩ,带宽4.7 GHz;等效输入噪声30.1 p A/Hz,眼图迹线清晰,张开度较大,能够满足5 Gbps平衡光探测器通信要求。
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA10305)
文摘This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure to reduce the intersymbolinterference （ISI） of the communication chan nel. By employing inductive peaking technique for the highfrequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decisionfeedback equalizer optimizes the size of the CMLbased circuit such as D flipflops （DFF） and multiplex （MUX）, shortening the feedback path delay and speeding up the operation considerably. Designed in the 0. 181μm CMOS technology, the equalizer delivers 10Gb/s data over 18in FR4 trace with 28dB loss while drawing 27mW from a 1.8V supply. The overall chip area including pads is 0. 6 -0.7mm2.
文摘This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer （FFE） and a two-tap half-rate decision feedback equalizer （DFE） in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm^2.
文摘The performance of complementary metal oxide semiconductor(CMOS)circuits is affected by electromagnetic interference(EMI),and the study of the circuit's ability to resist EMI will facilitate the design of circuits with better performance.Current-mode CMOS circuits have been continuously developed in recent years due to their advantages of high speed and low power consumption over conventional circuits under the deep submicron process;their EMI resistance performance deserves further study.This paper introduces three kinds of NOT gate circuits:conventional voltage-mode CMOS,MOS current-mode logic(MCML)with voltage signal of input and output,and current-mode CMOS with current signal of input and output.The effects of EMI on three NOT gate circuits are investigated using Cadence Virtuoso software simulation,and a disturbance level factor is defined to compare the effects of different interference terminals,interference signals'waveforms,and interference signals'frequencies on the circuits in the 65 nm process.The relationship between input resistance and circuit EMI resistance performance is investigated by varying the value of cascade resistance at the input of the current-mode CMOS circuits.Simulation results show that the current-mode CMOS circuits have better resistance performance to EMI at high operating frequencies,and the higher the operating frequency of the current-mode CMOS circuits,the better the resistance performance of the circuits to EMI.Additionally,the effects of different temperatures and different processes on the resistance performance of three circuits are also studied.In the temperature range of-40℃to 125℃,the higher the temperature,the weaker the resistance ability of voltage-mode CMOS and MCML circuits,and the stronger the resistance ability of current-mode CMOS circuits.In the 28 nm process,the current-mode CMOS circuit interference resistance ability is relatively stronger than that of the other two kinds of circuits.The relative interference resistance ability of voltage-mode CMOS and MCML circuits in the 28 nm process is similar to that of the 65 nm process,while the relative interference resistance ability of current-mode CMOS circuits in the 28 nm process is stronger than that of the 65 nm process.This study provides a basis for the design of current-mode CMOS circuits against EMI.
基金Project supported by the National Basic Research Program of China(No.2010CB327404)the National Natural Science Foundation of China(No.60901012)
文摘A 37 GHz wide-band programmable divide-by-N frequency divider(FD) composed of a divide-by-2 divider(acting as the first stage) and a divider with a division ratio range of 273–330(acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider(with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic(DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as-20 d Bm at 32 GHz and the phase noise at 37 GHz is less than-130 d Bc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 m W at a supply voltage of 1.2 V and occupies an area of only 730 μm×475 μm.
