comparatorAbstract： A cryogenic successive approximation register （SAR） analog to digital converter （ADC） is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled fro...comparatorAbstract： A cryogenic successive approximation register （SAR） analog to digital converter （ADC） is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve the circuit＇s performance over this wide temperature range, a temperature-compensated time-based comparator architecture is used in the ADC, which provides a steady performance with ultra low power for extreme temperature （from room temperature down to 77 K） operation. The converter implemented in a standard 0.35 μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity （DNL） and 0.59 LSB maximum integral nonlinearity （1NL）. It achieves 9.3 bit effective number of bits （ENOB） with 200 kS/s sampling rate at 77 K, dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8 × 0.3 mm^2.展开更多
文摘comparatorAbstract： A cryogenic successive approximation register （SAR） analog to digital converter （ADC） is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve the circuit＇s performance over this wide temperature range, a temperature-compensated time-based comparator architecture is used in the ADC, which provides a steady performance with ultra low power for extreme temperature （from room temperature down to 77 K） operation. The converter implemented in a standard 0.35 μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity （DNL） and 0.59 LSB maximum integral nonlinearity （1NL）. It achieves 9.3 bit effective number of bits （ENOB） with 200 kS/s sampling rate at 77 K, dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8 × 0.3 mm^2.
