A constant loop bandwidth fractionalN frequency synthesizer for portable civilian global navigation satellite system （GNSS） receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work ing re...A constant loop bandwidth fractionalN frequency synthesizer for portable civilian global navigation satellite system （GNSS） receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work ing regions, the LCVCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized band width is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an inband phase noise lower than 93 dBc at a 10 kHz offset and a spur less than 70 dBc; the bandwidth varies by 4 3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area （without the LO tested buffer） is 0.5 mm2.展开更多
文摘A constant loop bandwidth fractionalN frequency synthesizer for portable civilian global navigation satellite system （GNSS） receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work ing regions, the LCVCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized band width is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an inband phase noise lower than 93 dBc at a 10 kHz offset and a spur less than 70 dBc; the bandwidth varies by 4 3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area （without the LO tested buffer） is 0.5 mm2.
