As computational complexity continues to increase,effectively designing a computation-inmemory(CIM)architecture has become a crucial task.In such an architecture,errors may occur due to factors such as voltage drift.T...As computational complexity continues to increase,effectively designing a computation-inmemory(CIM)architecture has become a crucial task.In such an architecture,errors may occur due to factors such as voltage drift.This work focuses on designing a simulation framework for In-Situ error correction of multi-bit memory-in-computing circuits.The research concentrates on In-Situ error correction techniques,allowing the system to instantly detect and correct errors during memory or computational operations at the same location where data is being processed and stored.The primary goal of this work is to explore how to minimize the impact of these errors on model accuracy.In constructing the simulation environment,multi-bit weights are decomposed,and 2D convolutions are decomposed into matrix multiplications,then mapped onto the CIM architecture.Based on this framework,this work further analyzes hardware errors in CIM,including the causes of errors,statistical characteristics,and the impact of extreme error values on accuracy.Furthermore,we introduce and deeply analyze clamping as an error correction technique.Through a series of simulations,we came to the following clear conclusion:To maximize hardware efficiency and accuracy correction effects,special attention must be paid to high-bit weights and the protection of sensitive convolutional layers.In addition,reasonable setting of clamping threshold and appropriate array-based output grouping strategy are also indispensable.These strategies provide clear optimization directions for neural networks in specific application scenarios.After considering the above strategies and optimizing,the model accuracy can reach a maximum of 73.8%,which is close to the baseline of 75.8%.Considering that the protection circuit area is reduced by 50%,this result shows excellent benefits.展开更多
Mathematical morphology operations are widely used in image processing such as defect analysis in semiconductor manufacturing and medical image analysis.These data-intensive applications have high requirements during ...Mathematical morphology operations are widely used in image processing such as defect analysis in semiconductor manufacturing and medical image analysis.These data-intensive applications have high requirements during hardware implementation that are challenging for conventional hardware platforms such as central processing units(CPUs)and graphics processing units(GPUs).Computation-in-memory(CIM)provides a possible solution for highly efficient morphology operations.In this study,we demonstrate the application of morphology operation with a novel memristor-based auto-detection architecture and demonstrate non-neuromoq)hic computation on a multi-array-based memristor system.Pixel-by-pixel logic computations with low parallelism are converted to parallel operations using memristors.Moreover,hardware-implemented computer-integrated manufacturing was used to experimentally demonstrate typical defect detection tasks in integrated circuit(IC)manufacturing and medical image analysis.In addition,we developed a new implementation scheme employing a four-layer network to realize small-object detection with high parallelism.The system benchmark based on the hardware measurement results showed significant improvement in the energy efficiency by approximately 358 times and 32 times more than when a CPU and GPU were employed,respectively,exhibiting the advantage of the proposed memristor-based morphology operation.展开更多
基金supported in part by NSTC,Taiwan,under Grant NSTC 114-2218-E-A49-031-MBK,Grant 112-2628-E-A49-021-MY3,and Grant 114-2634-FA49-001-.
文摘As computational complexity continues to increase,effectively designing a computation-inmemory(CIM)architecture has become a crucial task.In such an architecture,errors may occur due to factors such as voltage drift.This work focuses on designing a simulation framework for In-Situ error correction of multi-bit memory-in-computing circuits.The research concentrates on In-Situ error correction techniques,allowing the system to instantly detect and correct errors during memory or computational operations at the same location where data is being processed and stored.The primary goal of this work is to explore how to minimize the impact of these errors on model accuracy.In constructing the simulation environment,multi-bit weights are decomposed,and 2D convolutions are decomposed into matrix multiplications,then mapped onto the CIM architecture.Based on this framework,this work further analyzes hardware errors in CIM,including the causes of errors,statistical characteristics,and the impact of extreme error values on accuracy.Furthermore,we introduce and deeply analyze clamping as an error correction technique.Through a series of simulations,we came to the following clear conclusion:To maximize hardware efficiency and accuracy correction effects,special attention must be paid to high-bit weights and the protection of sensitive convolutional layers.In addition,reasonable setting of clamping threshold and appropriate array-based output grouping strategy are also indispensable.These strategies provide clear optimization directions for neural networks in specific application scenarios.After considering the above strategies and optimizing,the model accuracy can reach a maximum of 73.8%,which is close to the baseline of 75.8%.Considering that the protection circuit area is reduced by 50%,this result shows excellent benefits.
基金the National Natural Science Foundation of China(Grants No.92064001,61851404,and 61874169)the IoT Intelligent Microsystem Center of Tsinghua University-China Mobile Joint Research Institute.
文摘Mathematical morphology operations are widely used in image processing such as defect analysis in semiconductor manufacturing and medical image analysis.These data-intensive applications have high requirements during hardware implementation that are challenging for conventional hardware platforms such as central processing units(CPUs)and graphics processing units(GPUs).Computation-in-memory(CIM)provides a possible solution for highly efficient morphology operations.In this study,we demonstrate the application of morphology operation with a novel memristor-based auto-detection architecture and demonstrate non-neuromoq)hic computation on a multi-array-based memristor system.Pixel-by-pixel logic computations with low parallelism are converted to parallel operations using memristors.Moreover,hardware-implemented computer-integrated manufacturing was used to experimentally demonstrate typical defect detection tasks in integrated circuit(IC)manufacturing and medical image analysis.In addition,we developed a new implementation scheme employing a four-layer network to realize small-object detection with high parallelism.The system benchmark based on the hardware measurement results showed significant improvement in the energy efficiency by approximately 358 times and 32 times more than when a CPU and GPU were employed,respectively,exhibiting the advantage of the proposed memristor-based morphology operation.
