Subject Code:F01With the support by the National Natural Science Foundation of China,the research team led by Prof.Peng Lianmao(彭练矛)and Prof.Zhang Zhiyong(张志勇)at the Key Laboratory for the Physics and Chemistry ...Subject Code:F01With the support by the National Natural Science Foundation of China,the research team led by Prof.Peng Lianmao(彭练矛)and Prof.Zhang Zhiyong(张志勇)at the Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics,Peking University,Beijing,recently reported that carbon nanotube CMOS FETs were scaled down to the 5nm gate length and presented展开更多
Ge complementary tunneling field-effect transistors（TFETs） are fabricated with the NiGe metal source/drain（S/D） structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of suffi...Ge complementary tunneling field-effect transistors（TFETs） are fabricated with the NiGe metal source/drain（S/D） structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of sufficiently high Schottky barrier heights. As a result, the Ge p-and n-TFETs exhibit decent electrical properties of large ON-state current and steep sub-threshold slope（S factor）. Especially, I_d of 0.2 μA/μm is revealed at V_g-V_（th） = V_d = ±0.5 V for Ge pTFETs,with the S factor of 28 mV/dec at 7 K.展开更多
A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can b...A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.展开更多
Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of ...Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to rise.The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://irds.ieee.org/),but not publicly confirmed,indicating that more possibilities still exist.The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and speed.In this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances.And then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint.Under these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power consumption.This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”nodes.At the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power consumption.Further,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V CPUs.This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.展开更多
A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA（micro-electrode array） system are described. As a basic cell of the circuits, an OPA（ operation...A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA（micro-electrode array） system are described. As a basic cell of the circuits, an OPA（ operational amplifier） is designed with low power, low noise, small size and high gain. The detecting circuit has a chip area of 290 μm × 400 μm, a power dissipation of 2.02 mW, an equivalent input noise of 17.72 nV/ Hz, a gain of 60. 5 dB, and an output voltage from - 2. 48 to ＋ 2. 5 V. The stimulating circuit has a chip area of 130 μm × 290 μm, a power dissipation of 740 μW, and an output voltage from - 2. 5 to 2. 04 V. The parameters show that two circuits are suitable for a monolithic integrated MEA system. The detecting circuit and MEA have been fabricated. The test results show that the detecting circuit works well.展开更多
A low noise, high conversion gain down-conversion mixer for WLAN 802.11a applications, which adopts the high intermediate frequency （IF） topology, is presented. The input radio frequency （RF）band, local oscillator...A low noise, high conversion gain down-conversion mixer for WLAN 802.11a applications, which adopts the high intermediate frequency （IF） topology, is presented. The input radio frequency （RF）band, local oscillator（LO）frequency band and output IF are 5.15 to 5.35, 4.15 to 4.35 and 1 GHz, respectively. Source resistive degeneration technique and pseudo-differential Gilbert topology are used to achieve high linearity, and, current bleeding technique and LC resonant loads are used to acquire a low noise figure. In addition, the mixer adopts a common-source transistor pair cross-stacked with a source follow pair（CSSF）circuit as an output buffer to enhance the mixer＇s conversion gain but not deteriorate the other performances. The mixer is implemented in 0.18 μm RF CMOS（complementary metal oxide semiconductor transistor）technology and the chip area of the mixer including all bonding pads is 580 μm×1 185 μm. The measured results show that under a 1.8 V supply, the conversion gain is 10.1 dB; the input 1 dB compression point and the input-referred third-order intercept point are-3.5 and 5.3 dBm, respectively; the single side band （SSB）noise figure （NF）is 8.65 dB, and the core current consumption is 3.8 mA.展开更多
A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplific...A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.展开更多
A novel pulse stream neuron circuit is presented whose output pulse width facilitates sigmoid activation to activate the function of neurons. The wide symmetrical dynamic range of this neuron ensures high noise immuni...A novel pulse stream neuron circuit is presented whose output pulse width facilitates sigmoid activation to activate the function of neurons. The wide symmetrical dynamic range of this neuron ensures high noise immunity. The pulsed activation strategy provides a power efficient architecture, so the circuit has very low power dissipation. The simplicity of the circuit ensures its suitability for large-scale integration.展开更多
文摘Subject Code:F01With the support by the National Natural Science Foundation of China,the research team led by Prof.Peng Lianmao(彭练矛)and Prof.Zhang Zhiyong(张志勇)at the Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics,Peking University,Beijing,recently reported that carbon nanotube CMOS FETs were scaled down to the 5nm gate length and presented
基金Supported by the National Natural Science Foundation of China under Grant No 61504120the Zhejiang Provincial Natural Science Foundation of China under Grant No LR18F040001the Fundamental Research Funds for the Central Universities
文摘Ge complementary tunneling field-effect transistors（TFETs） are fabricated with the NiGe metal source/drain（S/D） structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of sufficiently high Schottky barrier heights. As a result, the Ge p-and n-TFETs exhibit decent electrical properties of large ON-state current and steep sub-threshold slope（S factor）. Especially, I_d of 0.2 μA/μm is revealed at V_g-V_（th） = V_d = ±0.5 V for Ge pTFETs,with the S factor of 28 mV/dec at 7 K.
文摘A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.
基金supported in part by STI 2030-Major Projects under Grant 2022ZD0209200in part by Beijing Natural Science Foundation-Xiaomi Innovation Joint Fund(L233009)+4 种基金in part by National Natural Science Foundation of China under Grant No.62374099in part by the Tsinghua-Toyota Joint Research Fundin part by the Daikin Tsinghua Union Programin part by Independent Research Program of School of Integrated Circuits,Tsinghua UniversityThis work was also sponsored by CIE-Tencent Robotics X Rhino-Bird Focused Research Program.
文摘Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to rise.The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://irds.ieee.org/),but not publicly confirmed,indicating that more possibilities still exist.The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and speed.In this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances.And then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint.Under these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power consumption.This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”nodes.At the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power consumption.Further,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V CPUs.This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.
基金The National Natural Science Foundation of China (No.90307013,90707005)the Natural Science Foundation of Jiangsu Province(No. BK2008032)Open Foundation of State Key Laboratory of Bio-Electronics of Southeast University
文摘A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA（micro-electrode array） system are described. As a basic cell of the circuits, an OPA（ operational amplifier） is designed with low power, low noise, small size and high gain. The detecting circuit has a chip area of 290 μm × 400 μm, a power dissipation of 2.02 mW, an equivalent input noise of 17.72 nV/ Hz, a gain of 60. 5 dB, and an output voltage from - 2. 48 to ＋ 2. 5 V. The stimulating circuit has a chip area of 130 μm × 290 μm, a power dissipation of 740 μW, and an output voltage from - 2. 5 to 2. 04 V. The parameters show that two circuits are suitable for a monolithic integrated MEA system. The detecting circuit and MEA have been fabricated. The test results show that the detecting circuit works well.
基金The Science and Technology Program of Zhejiang Province (No.2008C16017)
文摘A low noise, high conversion gain down-conversion mixer for WLAN 802.11a applications, which adopts the high intermediate frequency （IF） topology, is presented. The input radio frequency （RF）band, local oscillator（LO）frequency band and output IF are 5.15 to 5.35, 4.15 to 4.35 and 1 GHz, respectively. Source resistive degeneration technique and pseudo-differential Gilbert topology are used to achieve high linearity, and, current bleeding technique and LC resonant loads are used to acquire a low noise figure. In addition, the mixer adopts a common-source transistor pair cross-stacked with a source follow pair（CSSF）circuit as an output buffer to enhance the mixer＇s conversion gain but not deteriorate the other performances. The mixer is implemented in 0.18 μm RF CMOS（complementary metal oxide semiconductor transistor）technology and the chip area of the mixer including all bonding pads is 580 μm×1 185 μm. The measured results show that under a 1.8 V supply, the conversion gain is 10.1 dB; the input 1 dB compression point and the input-referred third-order intercept point are-3.5 and 5.3 dBm, respectively; the single side band （SSB）noise figure （NF）is 8.65 dB, and the core current consumption is 3.8 mA.
基金The National High Technology Research and Development Program of China(863 Program)(No.2007AA01Z2A7)
文摘A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.
基金Supported by the National Natural Science Foundationof China (No.6963 60 3 0)
文摘A novel pulse stream neuron circuit is presented whose output pulse width facilitates sigmoid activation to activate the function of neurons. The wide symmetrical dynamic range of this neuron ensures high noise immunity. The pulsed activation strategy provides a power efficient architecture, so the circuit has very low power dissipation. The simplicity of the circuit ensures its suitability for large-scale integration.
