Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detecti...Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detection performed using CMOS sensors. X-ray measurements were obtained using a simulated positioner based on a CMOS sensor, while the X-ray energy was modified by changing the voltage, current, and radiation time. A monitoring control unit collected video data of the detected X-rays. The video images were framed and filtered to detect the effective pixel points(radiation spots).The histograms of the images prove there is a linear relationship between the pixel points and X-ray energy. The relationships between the image pixel points, voltage, and current were quantified, and the resultant correlations were observed to obey some physical laws.展开更多
A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge...A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.展开更多
Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are ch...Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are characterized by X-ray photoemission spectroscopy, high-resolution transmission electron microscopy, capacitance-voltage （C-V） and current-voltage characteristics. It is demonstrated that wet thermal annealing at relatively higher temperature such as 550 ℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2, which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors. However, wet thermal annealing at 400 ℃ can decrease the GeOx interlayer thickness at the HfO2/Ge interface, resulting in a significant reduction of the interface states and a smaller effective oxide thickness, along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeOx in the wet ambient. The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C V characteristics for the as-prepared HfO2 gated Ge MOS capacitors, but it also dissembles the benefits of wet thermal annealing to a certain extent.展开更多
A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit ...A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit visible to near infra-red （NIR） light （the spectrum ranges from 500 nm to 1000 nm） in reverse bias avalanche breakdown mode with working voltage between 8.35 V-12 V and emit NIR light （the spectrum ranges from 900 nm to 1300 nm） in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.展开更多
Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of ...Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to rise.The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://irds.ieee.org/),but not publicly confirmed,indicating that more possibilities still exist.The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and speed.In this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances.And then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint.Under these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power consumption.This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”nodes.At the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power consumption.Further,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V CPUs.This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.展开更多
Two-dimensional(2D)transition metal dichalcogenides(TMDs),which allow atomic-scale manipulation,have supe-rior electrical and optical properties that challenge the limits of traditional bulk semiconductors like silico...Two-dimensional(2D)transition metal dichalcogenides(TMDs),which allow atomic-scale manipulation,have supe-rior electrical and optical properties that challenge the limits of traditional bulk semiconductors like silicon^([1,2]).As a repre-sentative TMD and a promising 2D channel material for high-performance,scalable p-type transistors,tungsten diselenide(WSe_(2))has attracted considerable academic and industrial interest for its potential in advanced complementary metal−oxide−semiconductor(CMOS)logic technology and in extending Moore’s Law^([3−7]).展开更多
A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM...A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.展开更多
The Complementary Metal-Oxide Semiconductor(CMOS)image sensor is a critical component with the function of providing accurate positioning in many space application systems.Under long-time operation in space environmen...The Complementary Metal-Oxide Semiconductor(CMOS)image sensor is a critical component with the function of providing accurate positioning in many space application systems.Under long-time operation in space environments,there are radiation related degradation and var-ious uncertainties affecting the positioning accuracy of CMOS image sensors,which further leads to a reliability reduction of CMOS image sensors.Obviously,the reliability of CMOS image sensors is related to their specified function,degradation,and uncertainties;however,current research has not fully described this relationship.In this paper,a comprehensive approach to reliability modelling of CMOs image sensors is proposed based on the reliability science principles.Firstly,the perfor-mance margin modelling of centroid positioning accuracy is conducted.Then,the degradation model of CMOS image sensors is derived considering the dark current increase induced by the total ionizing dose effects.Finally,various uncertainties are analyzed and quantified,and the measure-ment equation of reliability is proposed.A case study of a CMOS image sensor is conducted to apply the proposed method,and the sensitivity analysis can provide suggestions for design and use of CMOS image sensors to ensure reliability.A simulation study is conducted to present the advantages oftheproposed comprehensive approach.展开更多
为研究宇宙辐射环境中航天器里的模拟互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)集成电路性能和各种效应,并在辐射效应所产生机制的基础上,从设计和工艺方面提出了模拟CMOS集成电路主要抗辐射加固设计方法。...为研究宇宙辐射环境中航天器里的模拟互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)集成电路性能和各种效应,并在辐射效应所产生机制的基础上,从设计和工艺方面提出了模拟CMOS集成电路主要抗辐射加固设计方法。在宇宙环境中,卫星中的模拟CMOS集成电路存在CMOS半导体元器件阈值电压偏离、线性跨导减小、衬底的漏电流增加和转角1/f噪声幅值增加。所以提出了3种对模拟CMOS集成电路进行抗辐射加固的方法:1)抗辐射模拟CMOS集成电路的设计;2)抗辐射集成电路版图设计;3)单晶半导体硅膜(Silicon on Insulator,SOI)抗辐射工艺与加固设计。根据上面的设计方法研制了抗辐射加固模拟CMOS集成电路,可以取得较好的抗辐射效果。展开更多
基金supported by the Plan for Science Innovation Talent of Henan Province(No.154100510007)the Natural and Science Foundation in Henan Province(No.162300410179)the Cultivation Foundation of Henan Normal University National Project(No.2017PL04)
文摘Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detection performed using CMOS sensors. X-ray measurements were obtained using a simulated positioner based on a CMOS sensor, while the X-ray energy was modified by changing the voltage, current, and radiation time. A monitoring control unit collected video data of the detected X-rays. The video images were framed and filtered to detect the effective pixel points(radiation spots).The histograms of the images prove there is a linear relationship between the pixel points and X-ray energy. The relationships between the image pixel points, voltage, and current were quantified, and the resultant correlations were observed to obey some physical laws.
基金supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2010ZX02201)the National Natural Science Foundation of China (Grant No. 61176069)the National Defense Pre-Research of China (Grant No. 51308020304)
文摘A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61176092,61036003,and 60837001)the National Basic Research Program of China (Grant No. 2012CB933503)+1 种基金the Ph.D. Program Foundation of Ministry of Education of China (Grant No. 20110121110025)the Fundamental Research Funds for the Central Universities,China (Grant No. 2010121056)
文摘Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are characterized by X-ray photoemission spectroscopy, high-resolution transmission electron microscopy, capacitance-voltage （C-V） and current-voltage characteristics. It is demonstrated that wet thermal annealing at relatively higher temperature such as 550 ℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2, which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors. However, wet thermal annealing at 400 ℃ can decrease the GeOx interlayer thickness at the HfO2/Ge interface, resulting in a significant reduction of the interface states and a smaller effective oxide thickness, along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeOx in the wet ambient. The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C V characteristics for the as-prepared HfO2 gated Ge MOS capacitors, but it also dissembles the benefits of wet thermal annealing to a certain extent.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60536030,61036002,60776024,60877035 and 61036009)National High Technology Research and Development Program of China(Grant Nos.2007AA04Z329 and 2007AA04Z254)
文摘A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit visible to near infra-red （NIR） light （the spectrum ranges from 500 nm to 1000 nm） in reverse bias avalanche breakdown mode with working voltage between 8.35 V-12 V and emit NIR light （the spectrum ranges from 900 nm to 1300 nm） in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.
基金supported in part by STI 2030-Major Projects under Grant 2022ZD0209200in part by Beijing Natural Science Foundation-Xiaomi Innovation Joint Fund(L233009)+4 种基金in part by National Natural Science Foundation of China under Grant No.62374099in part by the Tsinghua-Toyota Joint Research Fundin part by the Daikin Tsinghua Union Programin part by Independent Research Program of School of Integrated Circuits,Tsinghua UniversityThis work was also sponsored by CIE-Tencent Robotics X Rhino-Bird Focused Research Program.
文摘Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to rise.The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://irds.ieee.org/),but not publicly confirmed,indicating that more possibilities still exist.The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and speed.In this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances.And then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint.Under these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power consumption.This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”nodes.At the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power consumption.Further,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V CPUs.This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.
文摘Two-dimensional(2D)transition metal dichalcogenides(TMDs),which allow atomic-scale manipulation,have supe-rior electrical and optical properties that challenge the limits of traditional bulk semiconductors like silicon^([1,2]).As a repre-sentative TMD and a promising 2D channel material for high-performance,scalable p-type transistors,tungsten diselenide(WSe_(2))has attracted considerable academic and industrial interest for its potential in advanced complementary metal−oxide−semiconductor(CMOS)logic technology and in extending Moore’s Law^([3−7]).
基金The National Natural Science Foundation of China(No. 61106024)the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20090092120012)the Science and Technology Program of South east University (No. KJ2010402)
文摘A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.
基金the National Natural Science Foundation of China (No.51775020)the Science Challenge Project,China (No.TZ2018007)+1 种基金the National Natural Science Foundation of China (No.62073009)the Fundamental Research Funds for Central Universities,China (No.YWF-19-BJ-J-515).
文摘The Complementary Metal-Oxide Semiconductor(CMOS)image sensor is a critical component with the function of providing accurate positioning in many space application systems.Under long-time operation in space environments,there are radiation related degradation and var-ious uncertainties affecting the positioning accuracy of CMOS image sensors,which further leads to a reliability reduction of CMOS image sensors.Obviously,the reliability of CMOS image sensors is related to their specified function,degradation,and uncertainties;however,current research has not fully described this relationship.In this paper,a comprehensive approach to reliability modelling of CMOs image sensors is proposed based on the reliability science principles.Firstly,the perfor-mance margin modelling of centroid positioning accuracy is conducted.Then,the degradation model of CMOS image sensors is derived considering the dark current increase induced by the total ionizing dose effects.Finally,various uncertainties are analyzed and quantified,and the measure-ment equation of reliability is proposed.A case study of a CMOS image sensor is conducted to apply the proposed method,and the sensitivity analysis can provide suggestions for design and use of CMOS image sensors to ensure reliability.A simulation study is conducted to present the advantages oftheproposed comprehensive approach.
文摘为研究宇宙辐射环境中航天器里的模拟互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)集成电路性能和各种效应,并在辐射效应所产生机制的基础上,从设计和工艺方面提出了模拟CMOS集成电路主要抗辐射加固设计方法。在宇宙环境中,卫星中的模拟CMOS集成电路存在CMOS半导体元器件阈值电压偏离、线性跨导减小、衬底的漏电流增加和转角1/f噪声幅值增加。所以提出了3种对模拟CMOS集成电路进行抗辐射加固的方法:1)抗辐射模拟CMOS集成电路的设计;2)抗辐射集成电路版图设计;3)单晶半导体硅膜(Silicon on Insulator,SOI)抗辐射工艺与加固设计。根据上面的设计方法研制了抗辐射加固模拟CMOS集成电路,可以取得较好的抗辐射效果。
