Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detecti...Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detection performed using CMOS sensors. X-ray measurements were obtained using a simulated positioner based on a CMOS sensor, while the X-ray energy was modified by changing the voltage, current, and radiation time. A monitoring control unit collected video data of the detected X-rays. The video images were framed and filtered to detect the effective pixel points(radiation spots).The histograms of the images prove there is a linear relationship between the pixel points and X-ray energy. The relationships between the image pixel points, voltage, and current were quantified, and the resultant correlations were observed to obey some physical laws.展开更多
A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge...A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.展开更多
Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are ch...Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are characterized by X-ray photoemission spectroscopy, high-resolution transmission electron microscopy, capacitance-voltage （C-V） and current-voltage characteristics. It is demonstrated that wet thermal annealing at relatively higher temperature such as 550 ℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2, which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors. However, wet thermal annealing at 400 ℃ can decrease the GeOx interlayer thickness at the HfO2/Ge interface, resulting in a significant reduction of the interface states and a smaller effective oxide thickness, along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeOx in the wet ambient. The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C V characteristics for the as-prepared HfO2 gated Ge MOS capacitors, but it also dissembles the benefits of wet thermal annealing to a certain extent.展开更多
A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit ...A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit visible to near infra-red （NIR） light （the spectrum ranges from 500 nm to 1000 nm） in reverse bias avalanche breakdown mode with working voltage between 8.35 V-12 V and emit NIR light （the spectrum ranges from 900 nm to 1300 nm） in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.展开更多
文中设计了一种宽带低相位噪声压控振荡器(VCO)。该VCO采用了基于周期性时变电感的Class-D结构,并将共模谐振扩展技术应用于谐振腔,实现了宽带谐波整形,优化了整个带宽内的相位噪声性能。此外,将传统的N沟道金属氧化物半导体对替换为P...文中设计了一种宽带低相位噪声压控振荡器(VCO)。该VCO采用了基于周期性时变电感的Class-D结构,并将共模谐振扩展技术应用于谐振腔,实现了宽带谐波整形,优化了整个带宽内的相位噪声性能。此外,将传统的N沟道金属氧化物半导体对替换为P沟道金属氧化物半导体交叉耦合对,降低了沟道电流的热噪声与闪烁噪声。该芯片采用SMIC 55-nm CMOS工艺制造,包括焊盘在内的芯片面积为0.47 mm^(2)。测试结果表明,该VCO芯片在3.5 GHz~5.1 GHz(38.4%)的宽频率范围内能连续工作,输出功率为7.5 d Bm~7.1 d Bm,其在3.5 GHz处测试的相位噪声为-125.8 d Bc/Hz@1 MHz。当电源电压为1.8 V时,该VCO核心消耗电流为21.3 m A~23.0 m A,缓冲级消耗电流为14.4 m A~15.3 m A,对应含调谐范围的优值(Fo MT)为192.4 d Bc/Hz~189.6 d Bc/Hz。展开更多
基于高速低功耗混合应用场景下对互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)比较器性能的综合需求,系统研究其结构优化设计。阐述动态比较器在响应速度、功耗控制、输入失调与噪声抑制等方面的关键技术,介绍...基于高速低功耗混合应用场景下对互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)比较器性能的综合需求,系统研究其结构优化设计。阐述动态比较器在响应速度、功耗控制、输入失调与噪声抑制等方面的关键技术,介绍前置放大器、电源控制、闭环反馈及偏置电路的协同优化策略。结合65 nm CMOS工艺下的仿真测试结果,分析主要性能指标在典型工况下的表现,验证所提结构的可实现性与工程适应性。结果表明,该设计能够在低功耗约束下保持高速响应。展开更多
Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of ...Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to rise.The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://irds.ieee.org/),but not publicly confirmed,indicating that more possibilities still exist.The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and speed.In this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances.And then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint.Under these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power consumption.This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”nodes.At the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power consumption.Further,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V CPUs.This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.展开更多
Two-dimensional(2D)transition metal dichalcogenides(TMDs),which allow atomic-scale manipulation,have supe-rior electrical and optical properties that challenge the limits of traditional bulk semiconductors like silico...Two-dimensional(2D)transition metal dichalcogenides(TMDs),which allow atomic-scale manipulation,have supe-rior electrical and optical properties that challenge the limits of traditional bulk semiconductors like silicon^([1,2]).As a repre-sentative TMD and a promising 2D channel material for high-performance,scalable p-type transistors,tungsten diselenide(WSe_(2))has attracted considerable academic and industrial interest for its potential in advanced complementary metal−oxide−semiconductor(CMOS)logic technology and in extending Moore’s Law^([3−7]).展开更多
基金supported by the Plan for Science Innovation Talent of Henan Province(No.154100510007)the Natural and Science Foundation in Henan Province(No.162300410179)the Cultivation Foundation of Henan Normal University National Project(No.2017PL04)
文摘Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detection performed using CMOS sensors. X-ray measurements were obtained using a simulated positioner based on a CMOS sensor, while the X-ray energy was modified by changing the voltage, current, and radiation time. A monitoring control unit collected video data of the detected X-rays. The video images were framed and filtered to detect the effective pixel points(radiation spots).The histograms of the images prove there is a linear relationship between the pixel points and X-ray energy. The relationships between the image pixel points, voltage, and current were quantified, and the resultant correlations were observed to obey some physical laws.
基金supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2010ZX02201)the National Natural Science Foundation of China (Grant No. 61176069)the National Defense Pre-Research of China (Grant No. 51308020304)
文摘A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61176092,61036003,and 60837001)the National Basic Research Program of China (Grant No. 2012CB933503)+1 种基金the Ph.D. Program Foundation of Ministry of Education of China (Grant No. 20110121110025)the Fundamental Research Funds for the Central Universities,China (Grant No. 2010121056)
文摘Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are characterized by X-ray photoemission spectroscopy, high-resolution transmission electron microscopy, capacitance-voltage （C-V） and current-voltage characteristics. It is demonstrated that wet thermal annealing at relatively higher temperature such as 550 ℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2, which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors. However, wet thermal annealing at 400 ℃ can decrease the GeOx interlayer thickness at the HfO2/Ge interface, resulting in a significant reduction of the interface states and a smaller effective oxide thickness, along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeOx in the wet ambient. The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C V characteristics for the as-prepared HfO2 gated Ge MOS capacitors, but it also dissembles the benefits of wet thermal annealing to a certain extent.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60536030,61036002,60776024,60877035 and 61036009)National High Technology Research and Development Program of China(Grant Nos.2007AA04Z329 and 2007AA04Z254)
文摘A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit visible to near infra-red （NIR） light （the spectrum ranges from 500 nm to 1000 nm） in reverse bias avalanche breakdown mode with working voltage between 8.35 V-12 V and emit NIR light （the spectrum ranges from 900 nm to 1300 nm） in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.
文摘微通道板行波选通分幅相机常用于惯性约束聚变,存在体积庞大和非单视线成像等问题,可以采用互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)图像传感器(CMOS image sensor,CIS)替代微通道板变像管的方式来解决这些问题.基于0.18µm标准CMOS工艺,提出一种8×8像素阵列的CMOS图像传感器设计方案.通过设计超短快门像素电路和快门信号控制电路,实现单次4分幅成像,并采用基于单端放大器的相关双采样电路消除噪声.仿真结果表明,该电路功能正常,4幅图像像素信号均匀性优于99%,每幅图像时间分辨率为100 ps,画幅时间间隔为300 ps.
文摘文中设计了一种宽带低相位噪声压控振荡器(VCO)。该VCO采用了基于周期性时变电感的Class-D结构,并将共模谐振扩展技术应用于谐振腔,实现了宽带谐波整形,优化了整个带宽内的相位噪声性能。此外,将传统的N沟道金属氧化物半导体对替换为P沟道金属氧化物半导体交叉耦合对,降低了沟道电流的热噪声与闪烁噪声。该芯片采用SMIC 55-nm CMOS工艺制造,包括焊盘在内的芯片面积为0.47 mm^(2)。测试结果表明,该VCO芯片在3.5 GHz~5.1 GHz(38.4%)的宽频率范围内能连续工作,输出功率为7.5 d Bm~7.1 d Bm,其在3.5 GHz处测试的相位噪声为-125.8 d Bc/Hz@1 MHz。当电源电压为1.8 V时,该VCO核心消耗电流为21.3 m A~23.0 m A,缓冲级消耗电流为14.4 m A~15.3 m A,对应含调谐范围的优值(Fo MT)为192.4 d Bc/Hz~189.6 d Bc/Hz。
基金supported in part by STI 2030-Major Projects under Grant 2022ZD0209200in part by Beijing Natural Science Foundation-Xiaomi Innovation Joint Fund(L233009)+4 种基金in part by National Natural Science Foundation of China under Grant No.62374099in part by the Tsinghua-Toyota Joint Research Fundin part by the Daikin Tsinghua Union Programin part by Independent Research Program of School of Integrated Circuits,Tsinghua UniversityThis work was also sponsored by CIE-Tencent Robotics X Rhino-Bird Focused Research Program.
文摘Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to rise.The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://irds.ieee.org/),but not publicly confirmed,indicating that more possibilities still exist.The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and speed.In this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances.And then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint.Under these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power consumption.This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”nodes.At the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power consumption.Further,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V CPUs.This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.
文摘Two-dimensional(2D)transition metal dichalcogenides(TMDs),which allow atomic-scale manipulation,have supe-rior electrical and optical properties that challenge the limits of traditional bulk semiconductors like silicon^([1,2]).As a repre-sentative TMD and a promising 2D channel material for high-performance,scalable p-type transistors,tungsten diselenide(WSe_(2))has attracted considerable academic and industrial interest for its potential in advanced complementary metal−oxide−semiconductor(CMOS)logic technology and in extending Moore’s Law^([3−7]).
