Edge devices,due to their limited computational and storage resources,often require the use of compilers for program optimization.Therefore,ensuring the security and reliability of these compilers is of paramount impo...Edge devices,due to their limited computational and storage resources,often require the use of compilers for program optimization.Therefore,ensuring the security and reliability of these compilers is of paramount importance in the emerging field of edge AI.One widely used testing method for this purpose is fuzz testing,which detects bugs by inputting random test cases into the target program.However,this process consumes significant time and resources.To improve the efficiency of compiler fuzz testing,it is common practice to utilize test case prioritization techniques.Some researchers use machine learning to predict the code coverage of test cases,aiming to maximize the test capability for the target compiler by increasing the overall predicted coverage of the test cases.Nevertheless,these methods can only forecast the code coverage of the compiler at a specific optimization level,potentially missing many optimization-related bugs.In this paper,we introduce C-CORE(short for Clustering by Code Representation),the first framework to prioritize test cases according to their code representations,which are derived directly from the source codes.This approach avoids being limited to specific compiler states and extends to a broader range of compiler bugs.Specifically,we first train a scaled pre-trained programming language model to capture as many common features as possible from the test cases generated by a fuzzer.Using this pre-trained model,we then train two downstream models:one for predicting the likelihood of triggering a bug and another for identifying code representations associated with bugs.Subsequently,we cluster the test cases according to their code representations and select the highest-scoring test case from each cluster as the high-quality test case.This reduction in redundant testing cases leads to time savings.Comprehensive evaluation results reveal that code representations are better at distinguishing test capabilities,and C-CORE significantly enhances testing efficiency.Across four datasets,C-CORE increases the average of the percentage of faults detected(APFD)value by 0.16 to 0.31 and reduces test time by over 50% in 46% of cases.When compared to the best results from approaches using predicted code coverage,C-CORE improves the APFD value by 1.1% to 12.3% and achieves an overall time-saving of 159.1%.展开更多
In order to adapt different languages and platforms, the paper discusses how to process and validate IDL symbol table and intermediate code by XML API. It puts emphasis on IDL AP1 extension towards DOM API based on th...In order to adapt different languages and platforms, the paper discusses how to process and validate IDL symbol table and intermediate code by XML API. It puts emphasis on IDL AP1 extension towards DOM API based on the idea of combining XML with IDL compilers. At last, the IDL compiler designing framework based on XML AP! is given, in which compiler front end can be managed and validated by some XML techniques and tools, IDL API can be validated on the basis of test, so IDL intermediate code is provided with maintainability, portability and generation. IDL compiler can be developed and extended by XML-based API, which realizes versatility and portability of modern compiler.展开更多
A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly...A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.展开更多
Syntax Notation One (ASN.1) has been widely used in specifications of high level communication protocol. It is also very important for Intelligent Networks Application Protocol(INAP). This paper presents the design an...Syntax Notation One (ASN.1) has been widely used in specifications of high level communication protocol. It is also very important for Intelligent Networks Application Protocol(INAP). This paper presents the design and implementation of the ASN.1 C++ compiler. According to the ASN.1 text, this compiler can generate C++ code of functions for encoding and decoding the data types which are defined by ASN.1. These functions are based on the Basic Encoding Rules(BER) of ASN.1. They have been used in the CIN 01 and CIN 02 systems.展开更多
The paper addresses the challenge of transmitting a big number offiles stored in a data center(DC),encrypting them by compilers,and sending them through a network at an acceptable time.Face to the big number offiles,o...The paper addresses the challenge of transmitting a big number offiles stored in a data center(DC),encrypting them by compilers,and sending them through a network at an acceptable time.Face to the big number offiles,only one compiler may not be sufficient to encrypt data in an acceptable time.In this paper,we consider the problem of several compilers and the objective is tofind an algorithm that can give an efficient schedule for the givenfiles to be compiled by the compilers.The main objective of the work is to minimize the gap in the total size of assignedfiles between compilers.This minimization ensures the fair distribution offiles to different compilers.This problem is considered to be a very hard problem.This paper presents two research axes.Thefirst axis is related to architecture.We propose a novel pre-compiler architecture in this context.The second axis is algorithmic development.We develop six algorithms to solve the problem,in this context.These algorithms are based on the dispatching rules method,decomposition method,and an iterative approach.These algorithms give approximate solutions for the studied problem.An experimental result is imple-mented to show the performance of algorithms.Several indicators are used to measure the performance of the proposed algorithms.In addition,five classes are proposed to test the algorithms with a total of 2350 instances.A comparison between the proposed algorithms is presented in different tables discussed to show the performance of each algorithm.The result showed that the best algorithm is the Iterative-mixed Smallest-Longest-Heuristic(ISL)with a percentage equal to 97.7%and an average running time equal to 0.148 s.All other algorithms did not exceed 22%as a percentage.The best algorithm excluding ISL is Iterative-mixed Longest-Smallest Heuristic(ILS)with a percentage equal to 21,4%and an average running time equal to 0.150 s.展开更多
An object-oriented C++ parallel compiler System, called OOCPCS, is developed to facilitate programmers to write sequential programs using C++ or Annotated C++ language for parallel computahon. OOCPCS bases on an integ...An object-oriented C++ parallel compiler System, called OOCPCS, is developed to facilitate programmers to write sequential programs using C++ or Annotated C++ language for parallel computahon. OOCPCS bases on an integrated object-oriented paradigm and large-grain data flow model, called OOLGDFM, and recognizes automatically parallel objects using parallel compiling techniques. The paper describes the object-oriented parallel model and realization of the System on networks.展开更多
The paper’s purpose is to design and program the four operation-calculators that receives voice instructions and runs them as either a voice or text phase. The Calculator simulates the work of the Compiler. The paper...The paper’s purpose is to design and program the four operation-calculators that receives voice instructions and runs them as either a voice or text phase. The Calculator simulates the work of the Compiler. The paper is a practical <span style="font-family:Verdana;">example programmed to support that it is possible to construct a verbal</span><span style="font-family:Verdana;"> Compiler.</span>展开更多
With the continuous expansion of software applications,people’s requirements for software quality are increasing.Software defect prediction is an important technology to improve software quality.It often encodes the ...With the continuous expansion of software applications,people’s requirements for software quality are increasing.Software defect prediction is an important technology to improve software quality.It often encodes the software into several features and applies the machine learning method to build defect prediction classifiers,which can estimate the software areas is clean or buggy.However,the current encoding methods are mainly based on the traditional manual features or the AST of source code.Traditional manual features are difficult to reflect the deep semantics of programs,and there is a lot of noise information in AST,which affects the expression of semantic features.To overcome the above deficiencies,we combined with the Convolutional Neural Networks(CNN)and proposed a novel compiler Intermediate Representation(IR)based program encoding method for software defect prediction(CIR-CNN).Specifically,our program encoding method is based on the compiler IR,which can eliminate a large amount of noise information in the syntax structure of the source code and facilitate the acquisition of more accurate semantic information.Secondly,with the help of data flow analysis,a Data Dependency Graph(DDG)is constructed on the compiler IR,which helps to capture the deeper semantic information of the program.Finally,we use the widely used CNN model to build a software defect prediction model,which can increase the adaptive ability of the method.To evaluate the performance of the CIR-CNN,we use seven projects from PROMISE datasets to set up comparative experiments.The experiments results show that,in WPDP,with our CIR-CNN method,the prediction accuracy was improved by 12%for the AST-encoded CNN-based model and by 20.9%for the traditional features-based LR model,respectively.And in CPDP,the AST-encoded DBNbased model was improved by 9.1%and the traditional features-based TCA+model by 19.2%,respectively.展开更多
The diversity of software and hardware forces programmers to spend a great deal of time optimizing their source code,which often requires specific treatment for each platform.The problem becomes critical on embedded d...The diversity of software and hardware forces programmers to spend a great deal of time optimizing their source code,which often requires specific treatment for each platform.The problem becomes critical on embedded devices,where computational and memory resources are strictly constrained.Compilers play an essential role in deploying source code on a target device through the backend.In this work,a novel backend for the Open Neural Network Compiler(ONNC)is proposed,which exploits machine learning to optimize code for the ARM Cortex-M device.The backend requires minimal changes to Open Neural Network Exchange(ONNX)models.Several novel optimization techniques are also incorporated in the backend,such as quantizing the ONNX model’s weight and automatically tuning the dimensions of operators in computations.The performance of the proposed framework is evaluated for two applications:handwritten digit recognition on the Modified National Institute of Standards and Technology(MNIST)dataset and model,and image classification on the Canadian Institute For Advanced Research and 10(CIFAR-10)dataset with the AlexNet-Light model.The system achieves 98.90%and 90.55%accuracy for handwritten digit recognition and image classification,respectively.Furthermore,the proposed architecture is significantly more lightweight than other state-of-theart models in terms of both computation time and generated source code complexity.From the system perspective,this work provides a novel approach to deploying direct computations from the available ONNX models to target devices by optimizing compilers while maintaining high efficiency in accuracy performance.展开更多
A new high-level langusge,B96,which is compiling-type and MCS-96 single chip computer series oriented ,has recently been designed and implemented by the authors. This paper discusses its design thought and its impleme...A new high-level langusge,B96,which is compiling-type and MCS-96 single chip computer series oriented ,has recently been designed and implemented by the authors. This paper discusses its design thought and its implementation. The paper also accounts for the design of B96/8096/8098 IDDEE,a software Integrated Debugging & Developing Environment of Emulation,which is used to debug and develop 8096/8098 assemble language and/or B96 high-level language source program on PC-based emulating platform.展开更多
VHDL and its supporting environment are active domain in the field of logic design.In the paper the design principle and some key techniques to solve the problems on the implementation of the VHDL parser are introduce...VHDL and its supporting environment are active domain in the field of logic design.In the paper the design principle and some key techniques to solve the problems on the implementation of the VHDL parser are introduced. According to the methods discussed in the paper, the VHDL parser based on VHDL IEEE 1076 standard version is implemented and a series of strict tests are done. This VHDL parser is front-end tool of the VHDL high level synthesis and mixed level simulation system developed by the Research Center of ASIC of BIT.展开更多
Since 2008, the author of this paper has conducted historiographic research on the visual history of science in the West since the mid-twentieth century. The findings show that the cognitive functions of visual scient...Since 2008, the author of this paper has conducted historiographic research on the visual history of science in the West since the mid-twentieth century. The findings show that the cognitive functions of visual scientific representations in the history of science are connected with theories of knowledge development in dialectical materialist epistemology and theories on children's cognitive features at different ages in developmental psychology, as well as the stage-specific curriculum objectives outlined in the Compulsory Education Science Curriculum Standards(2022 Edition). These insights provide essential inspiration and theoretical support for the establishment of the twin-theme logical structure in the Primary School Science Textbooks(Daxiang Edition)—core competencies as the warp and cognitive development as the weft—and for the intentional cultivation of students' cognitive abilities using scientific images across different learning stages and textbooks.展开更多
文摘Edge devices,due to their limited computational and storage resources,often require the use of compilers for program optimization.Therefore,ensuring the security and reliability of these compilers is of paramount importance in the emerging field of edge AI.One widely used testing method for this purpose is fuzz testing,which detects bugs by inputting random test cases into the target program.However,this process consumes significant time and resources.To improve the efficiency of compiler fuzz testing,it is common practice to utilize test case prioritization techniques.Some researchers use machine learning to predict the code coverage of test cases,aiming to maximize the test capability for the target compiler by increasing the overall predicted coverage of the test cases.Nevertheless,these methods can only forecast the code coverage of the compiler at a specific optimization level,potentially missing many optimization-related bugs.In this paper,we introduce C-CORE(short for Clustering by Code Representation),the first framework to prioritize test cases according to their code representations,which are derived directly from the source codes.This approach avoids being limited to specific compiler states and extends to a broader range of compiler bugs.Specifically,we first train a scaled pre-trained programming language model to capture as many common features as possible from the test cases generated by a fuzzer.Using this pre-trained model,we then train two downstream models:one for predicting the likelihood of triggering a bug and another for identifying code representations associated with bugs.Subsequently,we cluster the test cases according to their code representations and select the highest-scoring test case from each cluster as the high-quality test case.This reduction in redundant testing cases leads to time savings.Comprehensive evaluation results reveal that code representations are better at distinguishing test capabilities,and C-CORE significantly enhances testing efficiency.Across four datasets,C-CORE increases the average of the percentage of faults detected(APFD)value by 0.16 to 0.31 and reduces test time by over 50% in 46% of cases.When compared to the best results from approaches using predicted code coverage,C-CORE improves the APFD value by 1.1% to 12.3% and achieves an overall time-saving of 159.1%.
基金Supported by the Natural Science Foundation of Hubei Province (2005ABA266)the Natural Science Foundation of Henan Prov-ince (0611054800)
文摘In order to adapt different languages and platforms, the paper discusses how to process and validate IDL symbol table and intermediate code by XML API. It puts emphasis on IDL AP1 extension towards DOM API based on the idea of combining XML with IDL compilers. At last, the IDL compiler designing framework based on XML AP! is given, in which compiler front end can be managed and validated by some XML techniques and tools, IDL API can be validated on the basis of test, so IDL intermediate code is provided with maintainability, portability and generation. IDL compiler can be developed and extended by XML-based API, which realizes versatility and portability of modern compiler.
文摘A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.
文摘Syntax Notation One (ASN.1) has been widely used in specifications of high level communication protocol. It is also very important for Intelligent Networks Application Protocol(INAP). This paper presents the design and implementation of the ASN.1 C++ compiler. According to the ASN.1 text, this compiler can generate C++ code of functions for encoding and decoding the data types which are defined by ASN.1. These functions are based on the Basic Encoding Rules(BER) of ASN.1. They have been used in the CIN 01 and CIN 02 systems.
基金The author would like to thank the Deanship of Scientific Research at Majmaah University for supporting this work under Project Number No.R-2022-85.
文摘The paper addresses the challenge of transmitting a big number offiles stored in a data center(DC),encrypting them by compilers,and sending them through a network at an acceptable time.Face to the big number offiles,only one compiler may not be sufficient to encrypt data in an acceptable time.In this paper,we consider the problem of several compilers and the objective is tofind an algorithm that can give an efficient schedule for the givenfiles to be compiled by the compilers.The main objective of the work is to minimize the gap in the total size of assignedfiles between compilers.This minimization ensures the fair distribution offiles to different compilers.This problem is considered to be a very hard problem.This paper presents two research axes.Thefirst axis is related to architecture.We propose a novel pre-compiler architecture in this context.The second axis is algorithmic development.We develop six algorithms to solve the problem,in this context.These algorithms are based on the dispatching rules method,decomposition method,and an iterative approach.These algorithms give approximate solutions for the studied problem.An experimental result is imple-mented to show the performance of algorithms.Several indicators are used to measure the performance of the proposed algorithms.In addition,five classes are proposed to test the algorithms with a total of 2350 instances.A comparison between the proposed algorithms is presented in different tables discussed to show the performance of each algorithm.The result showed that the best algorithm is the Iterative-mixed Smallest-Longest-Heuristic(ISL)with a percentage equal to 97.7%and an average running time equal to 0.148 s.All other algorithms did not exceed 22%as a percentage.The best algorithm excluding ISL is Iterative-mixed Longest-Smallest Heuristic(ILS)with a percentage equal to 21,4%and an average running time equal to 0.150 s.
文摘An object-oriented C++ parallel compiler System, called OOCPCS, is developed to facilitate programmers to write sequential programs using C++ or Annotated C++ language for parallel computahon. OOCPCS bases on an integrated object-oriented paradigm and large-grain data flow model, called OOLGDFM, and recognizes automatically parallel objects using parallel compiling techniques. The paper describes the object-oriented parallel model and realization of the System on networks.
文摘The paper’s purpose is to design and program the four operation-calculators that receives voice instructions and runs them as either a voice or text phase. The Calculator simulates the work of the Compiler. The paper is a practical <span style="font-family:Verdana;">example programmed to support that it is possible to construct a verbal</span><span style="font-family:Verdana;"> Compiler.</span>
基金This work was supported by the Universities Natural Science Research Project of Jiangsu Province under Grant 20KJB520026 and 20KJA520002the Foundation for Young Teachers of Nanjing Auditing University under Grant 19QNPY018the National Nature Science Foundation of China under Grant 71972102 and 61902189.
文摘With the continuous expansion of software applications,people’s requirements for software quality are increasing.Software defect prediction is an important technology to improve software quality.It often encodes the software into several features and applies the machine learning method to build defect prediction classifiers,which can estimate the software areas is clean or buggy.However,the current encoding methods are mainly based on the traditional manual features or the AST of source code.Traditional manual features are difficult to reflect the deep semantics of programs,and there is a lot of noise information in AST,which affects the expression of semantic features.To overcome the above deficiencies,we combined with the Convolutional Neural Networks(CNN)and proposed a novel compiler Intermediate Representation(IR)based program encoding method for software defect prediction(CIR-CNN).Specifically,our program encoding method is based on the compiler IR,which can eliminate a large amount of noise information in the syntax structure of the source code and facilitate the acquisition of more accurate semantic information.Secondly,with the help of data flow analysis,a Data Dependency Graph(DDG)is constructed on the compiler IR,which helps to capture the deeper semantic information of the program.Finally,we use the widely used CNN model to build a software defect prediction model,which can increase the adaptive ability of the method.To evaluate the performance of the CIR-CNN,we use seven projects from PROMISE datasets to set up comparative experiments.The experiments results show that,in WPDP,with our CIR-CNN method,the prediction accuracy was improved by 12%for the AST-encoded CNN-based model and by 20.9%for the traditional features-based LR model,respectively.And in CPDP,the AST-encoded DBNbased model was improved by 9.1%and the traditional features-based TCA+model by 19.2%,respectively.
基金This work was supported in part by the Ministry of Science and Technology of Taiwan,R.O.C.,the Grant Number of project 108-2218-E-194-007.
文摘The diversity of software and hardware forces programmers to spend a great deal of time optimizing their source code,which often requires specific treatment for each platform.The problem becomes critical on embedded devices,where computational and memory resources are strictly constrained.Compilers play an essential role in deploying source code on a target device through the backend.In this work,a novel backend for the Open Neural Network Compiler(ONNC)is proposed,which exploits machine learning to optimize code for the ARM Cortex-M device.The backend requires minimal changes to Open Neural Network Exchange(ONNX)models.Several novel optimization techniques are also incorporated in the backend,such as quantizing the ONNX model’s weight and automatically tuning the dimensions of operators in computations.The performance of the proposed framework is evaluated for two applications:handwritten digit recognition on the Modified National Institute of Standards and Technology(MNIST)dataset and model,and image classification on the Canadian Institute For Advanced Research and 10(CIFAR-10)dataset with the AlexNet-Light model.The system achieves 98.90%and 90.55%accuracy for handwritten digit recognition and image classification,respectively.Furthermore,the proposed architecture is significantly more lightweight than other state-of-theart models in terms of both computation time and generated source code complexity.From the system perspective,this work provides a novel approach to deploying direct computations from the available ONNX models to target devices by optimizing compilers while maintaining high efficiency in accuracy performance.
基金The Project is supported by The Natural Science Fund of Jiangsu Province Education Committee.
文摘A new high-level langusge,B96,which is compiling-type and MCS-96 single chip computer series oriented ,has recently been designed and implemented by the authors. This paper discusses its design thought and its implementation. The paper also accounts for the design of B96/8096/8098 IDDEE,a software Integrated Debugging & Developing Environment of Emulation,which is used to debug and develop 8096/8098 assemble language and/or B96 high-level language source program on PC-based emulating platform.
文摘VHDL and its supporting environment are active domain in the field of logic design.In the paper the design principle and some key techniques to solve the problems on the implementation of the VHDL parser are introduced. According to the methods discussed in the paper, the VHDL parser based on VHDL IEEE 1076 standard version is implemented and a series of strict tests are done. This VHDL parser is front-end tool of the VHDL high level synthesis and mixed level simulation system developed by the Research Center of ASIC of BIT.
基金supported by a general research programme‘Research on the Compilation System of Primary School Science Textbooks with Marxist Epistemology as a Main Theme’under the 2023 Henan Province Education Sciences Plan launched by the Education Department of Henan Province(grant no.2023YB0610)
文摘Since 2008, the author of this paper has conducted historiographic research on the visual history of science in the West since the mid-twentieth century. The findings show that the cognitive functions of visual scientific representations in the history of science are connected with theories of knowledge development in dialectical materialist epistemology and theories on children's cognitive features at different ages in developmental psychology, as well as the stage-specific curriculum objectives outlined in the Compulsory Education Science Curriculum Standards(2022 Edition). These insights provide essential inspiration and theoretical support for the establishment of the twin-theme logical structure in the Primary School Science Textbooks(Daxiang Edition)—core competencies as the warp and cognitive development as the weft—and for the intentional cultivation of students' cognitive abilities using scientific images across different learning stages and textbooks.
