This article introduces a novel 20 V radiation-hardened high-voltage metal-oxide-semiconductor field-effect transistor(MOSFET)driver with an optimized input circuit and a drain-surrounding-source(DSS)structure.The inp...This article introduces a novel 20 V radiation-hardened high-voltage metal-oxide-semiconductor field-effect transistor(MOSFET)driver with an optimized input circuit and a drain-surrounding-source(DSS)structure.The input circuit of a conventional inverter consists of a thick-gate-oxide n-type MOSFET(NMOS).These conventional drivers can tolerate a total ionizing dose(TID)of up to 100 krad(Si).In contrast,the proposed comparator input circuit uses both a thick-gate-oxide p-type MOSFET(PMOS)and thin-gate-oxide NMOS to offer a high input voltage and higher TID tolerance.Because the thick-gate-oxide PMOS and thin-gate-oxide NMOS collectively provide better TID tolerance than the thick-gate-oxide NMOS,the circuit exhibits enhanced TID tolerance of>300 krad(Si).Simulations and experimental date indicate that the DSS structure reduces the probability of unwanted parasitic bipolar junction transistor activation,yielding a better single-event effect tolerance of over 81.8 MeVcm^(2)mg^(-1).The innovative strategy proposed in this study involves circuit and layout design optimization,and does not require any specialized process flow.Hence,the proposed circuit can be manufactured using common commercial 0.35μm BCD processes.展开更多
This paper presents a fully-differential CMOS dynamic comparator for use in high-speed pipelined ADCs with low stage resolution. Because the architecture is based on the coupled current sources and differential input ...This paper presents a fully-differential CMOS dynamic comparator for use in high-speed pipelined ADCs with low stage resolution. Because the architecture is based on the coupled current sources and differential input pairs, this comparator＇s threshold voltage can be adjusted to a desired level. Compared with traditional comparators, this one shows significant improvement in area,power,and speed. Fabricated in 0.35μm CMOS technology,it occupies only 30μm × 70μm. Simulation and measurement results indicate the comparator has a sampling frequency up to 1GHz with 2Vpp differential input signal range and only 181μW power consumption under a 3.3V supply. The speed/power ratio reaches up to 5524GS/J.展开更多
The capacity of the central nervous system for structural plasticity and regeneration is commonly believed to show a decreasing progression from“small and simple”brains to the larger,more complex brains of mammals.H...The capacity of the central nervous system for structural plasticity and regeneration is commonly believed to show a decreasing progression from“small and simple”brains to the larger,more complex brains of mammals.However,recent findings revealed that some forms of neural plasticity can show a reverse trend.Although plasticity is a well-preserved,transversal feature across the animal world,a variety of cell populations and mechanisms seem to have evolved to enable structural modifications to take place in widely different brains,likely as adaptations to selective pressures.Increasing evidence now indicates that a trade-off has occurred between regenerative(mostly stem cell–driven)plasticity and developmental(mostly juvenile)remodeling,with the latter primarily aimed not at brain repair but rather at“sculpting”the neural circuits based on experience.In particular,an evolutionary trade-off has occurred between neurogenic processes intended to support the possibility of recruiting new neurons throughout life and the different ways of obtaining new neurons,and between the different brain locations in which plasticity occurs.This review first briefly surveys the different types of plasticity and the complexity of their possible outcomes and then focuses on recent findings showing that the mammalian brain has a stem cell–independent integration of new neurons into pre-existing(mature)neural circuits.This process is still largely unknown but involves neuronal cells that have been blocked in arrested maturation since their embryonic origin(also termed“immature”or“dormant”neurons).These cells can then restart maturation throughout the animal's lifespan to become functional neurons in brain regions,such as the cerebral cortex and amygdala,that are relevant to high-order cognition and emotions.Unlike stem cell–driven postnatal/adult neurogenesis,which significantly decreases from small-brained,short-living species to large-brained ones,immature neurons are particularly abundant in large-brained,long-living mammals,including humans.The immature neural cell populations hosted in these complex brains are an interesting example of an“enlarged road”in the phylogenetic trend of plastic potential decreases commonly observed in the animal world.The topic of dormant neurons that covary with brain size and gyrencephaly represents a prospective turning point in the field of neuroplasticity,with important translational outcomes.These cells can represent a reservoir of undifferentiated neurons,potentially granting plasticity within the high-order circuits subserving the most sophisticated cognitive skills that are important in the growing brains of young,healthy individuals and are frequently affected by debilitating neurodevelopmental and degenerative disorders.展开更多
This paper presents an energy efficient successive-approximation register(SAR)analog-to-digital converter(ADC)for low-power applications.To improve the overall energy-efficiency,a skipping-window technique is used to ...This paper presents an energy efficient successive-approximation register(SAR)analog-to-digital converter(ADC)for low-power applications.To improve the overall energy-efficiency,a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator,which can provide not only the polarity of the input,but also the amount information of the input.The timedomain comparator,which is based on the edge pursing principle,consists of delay cells,two NAND gates,two D-flip-flop register-based phase detectors and a counter.The digital characteristic of the comparator makes the design more flexible,and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number.An energy efficient digital-to-analog converter(DAC)control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion.Together with the skipping-window technique,the linearity and the power consumption of the SAR ADC are improved.The impact of different window sizes on comparison cycles,DAC switching energy and the overall energy efficiency is analyzed.Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC,as well as the linearity,and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.展开更多
The demand of present technology inviting the popularity of multivalued optical computation system to coup up with the latest scenario of ultrahigh processing speed and handling large amount of data The magnitude comp...The demand of present technology inviting the popularity of multivalued optical computation system to coup up with the latest scenario of ultrahigh processing speed and handling large amount of data The magnitude comparator is the heart of the arithmetic and logic unit(ALU)in any logical processing and computing system.In this paper,a trinary magnitude comparator circuit has been proposed and implemented with modified trinary number(MTN)system.Optical tree architecture(OTA)of the proposed circuit has been realized reasonably using Savart plate and spatial light modulators(SLM).A simulation algorithm has also been developed and implemented to prove the authenticity of the proposed circuit through the simulation.展开更多
The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator ...The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.展开更多
The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 co...The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 comparator contains a controlled positive feedbackamplifier.Therefore,it is capable of realizing high speed and high precision.For improving theperformance and producibility,the tolerance extension,design centering and potential adaptingtechniques are used in the design of comparator ZJ03.展开更多
To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor(CMOS)technology developers.The scaling scenario is not an op...To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor(CMOS)technology developers.The scaling scenario is not an option nowadays and other technologies need to be investigated.The quantum-dot cellular automata(QCA)technology is one of the important emerging nanotechnologies that have attracted much researchers’attention in recent years.This technology has many interesting features,such as high speed,low power consumption,and small size.These features make it an appropriate alternative to the CMOS technique.This paper suggests three novel structures of XNOR gates in the QCA technology.The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology.The proposed structures are used as the main building blocks for a single-bit comparator.The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature.The comparison results are encouraging to append the proposed structures to the library of QCA gates.展开更多
It is vital segment to choose the right comparator product during the development and study of generic medicinal product, and this is also definitely specified in the relevant documents from the China Food and Drug Ad...It is vital segment to choose the right comparator product during the development and study of generic medicinal product, and this is also definitely specified in the relevant documents from the China Food and Drug Administration (CFDA)that the comparator product should be innovator product or internationally recognized same medicinal product,which is used in the re-evaluation of generic medicinal product or marketed authorization application of the generic medicinal product.To facilitate the domestic and foreign pharmaceutical enterprises to choose and determine comparator product,four medicinal product evaluation procedures,as well as the corresponding marketed medicinal product list,are detailed elaborated in this paper.At the same time, by taking the Mifepristone Tablet (200mg)as example,the search and determination process of the comparator product for generic medicinal product application in the EU is illustrated with the combination of different marketed medicinal product lists.展开更多
A novel design of multiplex differential voltage comparators(MDVC) is presented for reducing current and power dissipation. According to the special properties of relational operation and logical operation, parts of t...A novel design of multiplex differential voltage comparators(MDVC) is presented for reducing current and power dissipation. According to the special properties of relational operation and logical operation, parts of the comparators are redundant in some instances, and thus can be turned off. By selecting and switching the current routes, several effective differential pairs are biased by a single tail current stage-by-stage and the redundant comparators are turned off by cutting their tail currents. As a result, the quiescent current and power consumption are greatly decreased. The switching of current is achieved by the input differential pair transistors themselves and hence no extra switches are required. When a MDVC is used in a flash analog-to-digital converter(ADC), its current dissipation is much lower than that of the conventional comparators. This architecture can also be used in window-comparators, maximum or minimum comparators, and comparators for logical operations. The power dissipation in all these cases could be reduced significantly.展开更多
This paper presents a two-dimension time-domain comparator suitable for low power successive-approximation register(SAR)analog-to-digital converters(ADCs).The proposed two-dimension time-domain comparator consists of ...This paper presents a two-dimension time-domain comparator suitable for low power successive-approximation register(SAR)analog-to-digital converters(ADCs).The proposed two-dimension time-domain comparator consists of a ring oscillator collapse-based comparator and a counter.The propagation delay of a voltage controlled ring oscillator depends on the input.Thus,the comparator can automatically change the comparison time according to its input difference,which can adjust the power consumption of the comparator dynamically without any control logic.And a counter is utilized to count the cycle needed to finish a comparison when the input difference is small.Thus,the proposed comparator can not only provide the polarity of the input,but also the amount information of the input,which helps to skip most of the SAR cycles when the initial input is small.Thus,most energy can be saved when the initial input is small.The proposed time-domain comparator is designed in 0.18μm CMOS technology.Simulation results demonstrate that the comparator can not only save power consumption,but also give the design flexibility,and the current is only nA level when the supply voltage is 0.6 V.展开更多
In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as ...In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.展开更多
A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address ...A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.展开更多
There are magnetic interference problems in the applications of DC current comparator. Analysis on the magnetic effectiveness which is applied by the external magnetic field is introduced in this paper. The effectiven...There are magnetic interference problems in the applications of DC current comparator. Analysis on the magnetic effectiveness which is applied by the external magnetic field is introduced in this paper. The effectiveness is proved by the actual results which are compared with the magnetic- circuit method and the finite element method. In addition, the reference comment is given which can be used in the practical work of DC current comparator shield design.展开更多
背景由于其强大的语言处理能力和广泛的应用潜力,以ChatGPT为代表的大语言模型引领了医疗领域自然语言处理的新趋势。目的本研究通过文献计量分析揭示2017年以来医疗大语言模型的研究热点、主题分布及未来发展方向。方法通过Web of Scie...背景由于其强大的语言处理能力和广泛的应用潜力,以ChatGPT为代表的大语言模型引领了医疗领域自然语言处理的新趋势。目的本研究通过文献计量分析揭示2017年以来医疗大语言模型的研究热点、主题分布及未来发展方向。方法通过Web of Science、中国知网、万方数据知识服务平台和维普网数据库,系统检索和筛选2017年1月-2024年6月关于医疗大语言模型的文献。利用CiteSpace软件提取文献中的主题关键词等信息,分析并对比国内外研究的演进、热点和趋势。结果共纳入1071篇相关文献,结果显示国外研究集中于人工智能、大语言模型、深度学习、知识图谱等技术在医学中的应用,而国内研究则相对较少,侧重于中文医学问答系统构建和医疗数据非结构化问题处理。结论深化医疗数据挖掘,拓展多场景应用,并借鉴国际大语言模型的微调和应用评估经验,促进我国医疗大语言模型技术的发展和医学领域应用。展开更多
基金supported by the National Natural Science Foundation of China(U2241221).
文摘This article introduces a novel 20 V radiation-hardened high-voltage metal-oxide-semiconductor field-effect transistor(MOSFET)driver with an optimized input circuit and a drain-surrounding-source(DSS)structure.The input circuit of a conventional inverter consists of a thick-gate-oxide n-type MOSFET(NMOS).These conventional drivers can tolerate a total ionizing dose(TID)of up to 100 krad(Si).In contrast,the proposed comparator input circuit uses both a thick-gate-oxide p-type MOSFET(PMOS)and thin-gate-oxide NMOS to offer a high input voltage and higher TID tolerance.Because the thick-gate-oxide PMOS and thin-gate-oxide NMOS collectively provide better TID tolerance than the thick-gate-oxide NMOS,the circuit exhibits enhanced TID tolerance of>300 krad(Si).Simulations and experimental date indicate that the DSS structure reduces the probability of unwanted parasitic bipolar junction transistor activation,yielding a better single-event effect tolerance of over 81.8 MeVcm^(2)mg^(-1).The innovative strategy proposed in this study involves circuit and layout design optimization,and does not require any specialized process flow.Hence,the proposed circuit can be manufactured using common commercial 0.35μm BCD processes.
文摘This paper presents a fully-differential CMOS dynamic comparator for use in high-speed pipelined ADCs with low stage resolution. Because the architecture is based on the coupled current sources and differential input pairs, this comparator＇s threshold voltage can be adjusted to a desired level. Compared with traditional comparators, this one shows significant improvement in area,power,and speed. Fabricated in 0.35μm CMOS technology,it occupies only 30μm × 70μm. Simulation and measurement results indicate the comparator has a sampling frequency up to 1GHz with 2Vpp differential input signal range and only 181μW power consumption under a 3.3V supply. The speed/power ratio reaches up to 5524GS/J.
基金supported by Progetto Trapezio,Compagnia di San Paolo(67935-2021.2174),to LBFondazione CRT(Cassa di Risparmio di Torino,RF=2022.0618),to LBPRIN2022(grant 2022LB4X3N),to LB。
文摘The capacity of the central nervous system for structural plasticity and regeneration is commonly believed to show a decreasing progression from“small and simple”brains to the larger,more complex brains of mammals.However,recent findings revealed that some forms of neural plasticity can show a reverse trend.Although plasticity is a well-preserved,transversal feature across the animal world,a variety of cell populations and mechanisms seem to have evolved to enable structural modifications to take place in widely different brains,likely as adaptations to selective pressures.Increasing evidence now indicates that a trade-off has occurred between regenerative(mostly stem cell–driven)plasticity and developmental(mostly juvenile)remodeling,with the latter primarily aimed not at brain repair but rather at“sculpting”the neural circuits based on experience.In particular,an evolutionary trade-off has occurred between neurogenic processes intended to support the possibility of recruiting new neurons throughout life and the different ways of obtaining new neurons,and between the different brain locations in which plasticity occurs.This review first briefly surveys the different types of plasticity and the complexity of their possible outcomes and then focuses on recent findings showing that the mammalian brain has a stem cell–independent integration of new neurons into pre-existing(mature)neural circuits.This process is still largely unknown but involves neuronal cells that have been blocked in arrested maturation since their embryonic origin(also termed“immature”or“dormant”neurons).These cells can then restart maturation throughout the animal's lifespan to become functional neurons in brain regions,such as the cerebral cortex and amygdala,that are relevant to high-order cognition and emotions.Unlike stem cell–driven postnatal/adult neurogenesis,which significantly decreases from small-brained,short-living species to large-brained ones,immature neurons are particularly abundant in large-brained,long-living mammals,including humans.The immature neural cell populations hosted in these complex brains are an interesting example of an“enlarged road”in the phylogenetic trend of plastic potential decreases commonly observed in the animal world.The topic of dormant neurons that covary with brain size and gyrencephaly represents a prospective turning point in the field of neuroplasticity,with important translational outcomes.These cells can represent a reservoir of undifferentiated neurons,potentially granting plasticity within the high-order circuits subserving the most sophisticated cognitive skills that are important in the growing brains of young,healthy individuals and are frequently affected by debilitating neurodevelopmental and degenerative disorders.
基金This work was supported partly by the National Natural Science Foundation of China under Grant No.61704015the General program of Chongqing Natural Science Foundation(a special program for the fundamental and frontier research)under Grant No.cstc2019jcyj-msxmX0108.
文摘This paper presents an energy efficient successive-approximation register(SAR)analog-to-digital converter(ADC)for low-power applications.To improve the overall energy-efficiency,a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator,which can provide not only the polarity of the input,but also the amount information of the input.The timedomain comparator,which is based on the edge pursing principle,consists of delay cells,two NAND gates,two D-flip-flop register-based phase detectors and a counter.The digital characteristic of the comparator makes the design more flexible,and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number.An energy efficient digital-to-analog converter(DAC)control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion.Together with the skipping-window technique,the linearity and the power consumption of the SAR ADC are improved.The impact of different window sizes on comparison cycles,DAC switching energy and the overall energy efficiency is analyzed.Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC,as well as the linearity,and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.
文摘The demand of present technology inviting the popularity of multivalued optical computation system to coup up with the latest scenario of ultrahigh processing speed and handling large amount of data The magnitude comparator is the heart of the arithmetic and logic unit(ALU)in any logical processing and computing system.In this paper,a trinary magnitude comparator circuit has been proposed and implemented with modified trinary number(MTN)system.Optical tree architecture(OTA)of the proposed circuit has been realized reasonably using Savart plate and spatial light modulators(SLM).A simulation algorithm has also been developed and implemented to prove the authenticity of the proposed circuit through the simulation.
基金Supported by the National Natural Science Foundation of China (No. 60072004)
文摘The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.
文摘The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 comparator contains a controlled positive feedbackamplifier.Therefore,it is capable of realizing high speed and high precision.For improving theperformance and producibility,the tolerance extension,design centering and potential adaptingtechniques are used in the design of comparator ZJ03.
文摘To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor(CMOS)technology developers.The scaling scenario is not an option nowadays and other technologies need to be investigated.The quantum-dot cellular automata(QCA)technology is one of the important emerging nanotechnologies that have attracted much researchers’attention in recent years.This technology has many interesting features,such as high speed,low power consumption,and small size.These features make it an appropriate alternative to the CMOS technique.This paper suggests three novel structures of XNOR gates in the QCA technology.The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology.The proposed structures are used as the main building blocks for a single-bit comparator.The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature.The comparison results are encouraging to append the proposed structures to the library of QCA gates.
基金National Science and Technology Major Projects for ‘Major New Drugs Innovation and Development’(Grant No.2017ZX09101001,Beijing,China)
文摘It is vital segment to choose the right comparator product during the development and study of generic medicinal product, and this is also definitely specified in the relevant documents from the China Food and Drug Administration (CFDA)that the comparator product should be innovator product or internationally recognized same medicinal product,which is used in the re-evaluation of generic medicinal product or marketed authorization application of the generic medicinal product.To facilitate the domestic and foreign pharmaceutical enterprises to choose and determine comparator product,four medicinal product evaluation procedures,as well as the corresponding marketed medicinal product list,are detailed elaborated in this paper.At the same time, by taking the Mifepristone Tablet (200mg)as example,the search and determination process of the comparator product for generic medicinal product application in the EU is illustrated with the combination of different marketed medicinal product lists.
基金National Natural Science Foundation of China(60172004)PhD Subject Research Foundation of Ministry of Education of China(20010701003)
文摘A novel design of multiplex differential voltage comparators(MDVC) is presented for reducing current and power dissipation. According to the special properties of relational operation and logical operation, parts of the comparators are redundant in some instances, and thus can be turned off. By selecting and switching the current routes, several effective differential pairs are biased by a single tail current stage-by-stage and the redundant comparators are turned off by cutting their tail currents. As a result, the quiescent current and power consumption are greatly decreased. The switching of current is achieved by the input differential pair transistors themselves and hence no extra switches are required. When a MDVC is used in a flash analog-to-digital converter(ADC), its current dissipation is much lower than that of the conventional comparators. This architecture can also be used in window-comparators, maximum or minimum comparators, and comparators for logical operations. The power dissipation in all these cases could be reduced significantly.
基金This work was supported partly by the National Natural Science Foundation of China under grant No.61704015the General program of Chongqing Natural Science Foundation(a special program for the fundamental and frontier research)under grant No.cstc2019jcyj-msxmX0108.
文摘This paper presents a two-dimension time-domain comparator suitable for low power successive-approximation register(SAR)analog-to-digital converters(ADCs).The proposed two-dimension time-domain comparator consists of a ring oscillator collapse-based comparator and a counter.The propagation delay of a voltage controlled ring oscillator depends on the input.Thus,the comparator can automatically change the comparison time according to its input difference,which can adjust the power consumption of the comparator dynamically without any control logic.And a counter is utilized to count the cycle needed to finish a comparison when the input difference is small.Thus,the proposed comparator can not only provide the polarity of the input,but also the amount information of the input,which helps to skip most of the SAR cycles when the initial input is small.Thus,most energy can be saved when the initial input is small.The proposed time-domain comparator is designed in 0.18μm CMOS technology.Simulation results demonstrate that the comparator can not only save power consumption,but also give the design flexibility,and the current is only nA level when the supply voltage is 0.6 V.
文摘In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.
文摘A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.
文摘There are magnetic interference problems in the applications of DC current comparator. Analysis on the magnetic effectiveness which is applied by the external magnetic field is introduced in this paper. The effectiveness is proved by the actual results which are compared with the magnetic- circuit method and the finite element method. In addition, the reference comment is given which can be used in the practical work of DC current comparator shield design.
文摘背景由于其强大的语言处理能力和广泛的应用潜力,以ChatGPT为代表的大语言模型引领了医疗领域自然语言处理的新趋势。目的本研究通过文献计量分析揭示2017年以来医疗大语言模型的研究热点、主题分布及未来发展方向。方法通过Web of Science、中国知网、万方数据知识服务平台和维普网数据库,系统检索和筛选2017年1月-2024年6月关于医疗大语言模型的文献。利用CiteSpace软件提取文献中的主题关键词等信息,分析并对比国内外研究的演进、热点和趋势。结果共纳入1071篇相关文献,结果显示国外研究集中于人工智能、大语言模型、深度学习、知识图谱等技术在医学中的应用,而国内研究则相对较少,侧重于中文医学问答系统构建和医疗数据非结构化问题处理。结论深化医疗数据挖掘,拓展多场景应用,并借鉴国际大语言模型的微调和应用评估经验,促进我国医疗大语言模型技术的发展和医学领域应用。
