With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performanc...With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture （called Pianar-CRX）. Our Planar- CRX method integrates the extended deferred-merge embedding algorithm （DME-X, which extends the DME algorithm to X architecture） with modified Ohtsuki＇s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.展开更多
When IC technology is scaled into the very deep sub-micron regime, the optical proximity effects （OPE） turn into noticeable in optical lithography. Consequently, clock skew becomes more and more susceptible to proce...When IC technology is scaled into the very deep sub-micron regime, the optical proximity effects （OPE） turn into noticeable in optical lithography. Consequently, clock skew becomes more and more susceptible to process variations, such as OPE. In this paper, we propose a new buffered clock tree routing algorithm to prevent the influence of OPE and process variations to clock skew. Based on the concept of BSF （branch sensitivity factor）, our algorithm manages to reduce the skew sensitivity of the clock tree in the topology generation. The worst case skew due to the wire width change has been estimated, and proper buffers are inserted to avoid large capacitance load. Experimental results show that our algorithm can produce a more reliable, processinsensitive clock tree, and control clock skews in their permissible range evidently.展开更多
基金Supported in part by the National Natural Science Foundation of China (Grant No. 60876026), the Specialized Research Fund for the Doctoral Program of Higher Education (Crant No. 200800030026)
文摘With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture （called Pianar-CRX）. Our Planar- CRX method integrates the extended deferred-merge embedding algorithm （DME-X, which extends the DME algorithm to X architecture） with modified Ohtsuki＇s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.
基金the 863 National Hi-Tech Research and Development Plan of China(Grant No.2005AA1Z1230) the National Natural Science Foundation ofChina(Grant No.90307017).
文摘When IC technology is scaled into the very deep sub-micron regime, the optical proximity effects （OPE） turn into noticeable in optical lithography. Consequently, clock skew becomes more and more susceptible to process variations, such as OPE. In this paper, we propose a new buffered clock tree routing algorithm to prevent the influence of OPE and process variations to clock skew. Based on the concept of BSF （branch sensitivity factor）, our algorithm manages to reduce the skew sensitivity of the clock tree in the topology generation. The worst case skew due to the wire width change has been estimated, and proper buffers are inserted to avoid large capacitance load. Experimental results show that our algorithm can produce a more reliable, processinsensitive clock tree, and control clock skews in their permissible range evidently.
