In this paper, we propose a scheme for implementing the quantum clock synchronization （QCS） algorithm in cavity quantum electrodynamic （QED） formalism. Our method is based on three-level lader-type atoms interacti...In this paper, we propose a scheme for implementing the quantum clock synchronization （QCS） algorithm in cavity quantum electrodynamic （QED） formalism. Our method is based on three-level lader-type atoms interacting with classical and quantized cavity fields. Atom-qubit realizations of three-qubit and four-qubit QCS algorithms are explicitly presented.展开更多
Clock synchronization is a well-studied problem with many practical and scientific applications.We propose an arbitrary accuracy iterative quantum algorithm for distributed clock synchronization using only three qubit...Clock synchronization is a well-studied problem with many practical and scientific applications.We propose an arbitrary accuracy iterative quantum algorithm for distributed clock synchronization using only three qubits.The n bits of the time difference between two spatially separated clocks can be deterministically extracted by communicating only O（n） messages and executing the quantum iteration process n times based on the classical feedback and measurement operations.Finally,we also give the algorithm using only two qubits and discuss the success probability of the algorithm.展开更多
Influences of the clock resolution of bandwidth estimator on the accuracy and stability of the packet pair algorithm was analyzed.A mathematic model has been established to reveal the relationship between the result d...Influences of the clock resolution of bandwidth estimator on the accuracy and stability of the packet pair algorithm was analyzed.A mathematic model has been established to reveal the relationship between the result deviation coefficient and the packet size,clock resolution and real bandwidth(value)of the measured route.A bandwidth self-adapting packet pair algorithm was presented based on the mathematic model to reduce the estimation error resulting from the clock resolution and to improve the accuracy and stability of measurement by adjusting the deviation coefficient.Experimental results have verified the validity and stability of the algorithm.展开更多
The execution process of satellite-ground clock synchronization and ephemeris uploading in the system is analyzed,as well as their characterized operation and their relationship.Based on the analysis of the scheduling...The execution process of satellite-ground clock synchronization and ephemeris uploading in the system is analyzed,as well as their characterized operation and their relationship.Based on the analysis of the scheduling goal and constraint character,a heuristics rule-based multi-stage link scheduling algorithm was put forward.The algorithm distinguishes the on-off-frontier satellites from the others and schedules them by turns.The paper presented the main flow as well as the detailed design of the rule.Finally based on the current COMPASS global system,some typical resources and constraints are selected to generate an instance.Then the comparison analysis between the heuristics scheduling algorithm and three other traditional scheduling strategies are carried out.The result shows the validity and reasonability of the multi-stage strategy.展开更多
为满足雷达回波模拟器对时钟同步与同步时间安全性的需求,在现场可编程门阵列(Field Programmable Gate Array,FPGA)上采用精确时间协议(Precision Time Protocol,PTP)与SM4加密算法,实现回波模拟器之间的系统时钟同步,精确时间协议采用...为满足雷达回波模拟器对时钟同步与同步时间安全性的需求,在现场可编程门阵列(Field Programmable Gate Array,FPGA)上采用精确时间协议(Precision Time Protocol,PTP)与SM4加密算法,实现回波模拟器之间的系统时钟同步,精确时间协议采用PTPv2协议版本实现。在FPGA上设计PTP主时钟与从时钟模块,使回波模拟器在组网时可以通过实际需求由软件配置为PTP主时钟或从时钟;PTP主时钟控制引擎采用超时控制机制,防止PTP主时钟在时钟同步的交互过程中由于延迟请求报文异常,导致状态机卡死;时钟偏移的计算采用归一到纳秒的方式,提高时钟偏移的计算精度;采用SystemVerilog语言设计SM4加密算法的加密模块、解密模块,实现对时间戳信息的加密、解密,解决时间戳信息传输的安全性需求;采用“PTP over UDP over IPv4”方式在传输层对PTP协议报文进行封装,实现PTP报文通过以太网进行接收与发送。将时钟同步系统在AMD XC7K325TFFG676 FPGA芯片上进行设计实现,测试结果表明:该时钟同步系统性能稳定,且在直连情况下同步误差均小于500 ns,满足设计指标要求。展开更多
文摘In this paper, we propose a scheme for implementing the quantum clock synchronization （QCS） algorithm in cavity quantum electrodynamic （QED） formalism. Our method is based on three-level lader-type atoms interacting with classical and quantized cavity fields. Atom-qubit realizations of three-qubit and four-qubit QCS algorithms are explicitly presented.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 11147174 and 61068001)the Talent Program of Yanbian University,China (Grant No. 950010001)
文摘Clock synchronization is a well-studied problem with many practical and scientific applications.We propose an arbitrary accuracy iterative quantum algorithm for distributed clock synchronization using only three qubits.The n bits of the time difference between two spatially separated clocks can be deterministically extracted by communicating only O（n） messages and executing the quantum iteration process n times based on the classical feedback and measurement operations.Finally,we also give the algorithm using only two qubits and discuss the success probability of the algorithm.
基金This workis supported by973Project(National Keystone Foundation Research Project,No.G199903271)the National Natural Science Foundation of China(No.90104022)the National High Technology Development Program of China(No.2001AA112120,No.2002AA104550).
文摘Influences of the clock resolution of bandwidth estimator on the accuracy and stability of the packet pair algorithm was analyzed.A mathematic model has been established to reveal the relationship between the result deviation coefficient and the packet size,clock resolution and real bandwidth(value)of the measured route.A bandwidth self-adapting packet pair algorithm was presented based on the mathematic model to reduce the estimation error resulting from the clock resolution and to improve the accuracy and stability of measurement by adjusting the deviation coefficient.Experimental results have verified the validity and stability of the algorithm.
基金National Natural Science Foundations of China(Nos.71201171,71501179)
文摘The execution process of satellite-ground clock synchronization and ephemeris uploading in the system is analyzed,as well as their characterized operation and their relationship.Based on the analysis of the scheduling goal and constraint character,a heuristics rule-based multi-stage link scheduling algorithm was put forward.The algorithm distinguishes the on-off-frontier satellites from the others and schedules them by turns.The paper presented the main flow as well as the detailed design of the rule.Finally based on the current COMPASS global system,some typical resources and constraints are selected to generate an instance.Then the comparison analysis between the heuristics scheduling algorithm and three other traditional scheduling strategies are carried out.The result shows the validity and reasonability of the multi-stage strategy.
文摘为满足雷达回波模拟器对时钟同步与同步时间安全性的需求,在现场可编程门阵列(Field Programmable Gate Array,FPGA)上采用精确时间协议(Precision Time Protocol,PTP)与SM4加密算法,实现回波模拟器之间的系统时钟同步,精确时间协议采用PTPv2协议版本实现。在FPGA上设计PTP主时钟与从时钟模块,使回波模拟器在组网时可以通过实际需求由软件配置为PTP主时钟或从时钟;PTP主时钟控制引擎采用超时控制机制,防止PTP主时钟在时钟同步的交互过程中由于延迟请求报文异常,导致状态机卡死;时钟偏移的计算采用归一到纳秒的方式,提高时钟偏移的计算精度;采用SystemVerilog语言设计SM4加密算法的加密模块、解密模块,实现对时间戳信息的加密、解密,解决时间戳信息传输的安全性需求;采用“PTP over UDP over IPv4”方式在传输层对PTP协议报文进行封装,实现PTP报文通过以太网进行接收与发送。将时钟同步系统在AMD XC7K325TFFG676 FPGA芯片上进行设计实现,测试结果表明:该时钟同步系统性能稳定,且在直连情况下同步误差均小于500 ns,满足设计指标要求。
