This paper describes the study analysis performed to evaluate the available and potential solutions to control the highly increasing short circuit （SC） levels in Kuwait power system. The real Kuwait High Voltage （H...This paper describes the study analysis performed to evaluate the available and potential solutions to control the highly increasing short circuit （SC） levels in Kuwait power system. The real Kuwait High Voltage （HV） network was simulated to examine different measures at both 275 kV and 132 kV stations. The simulation results show that the short circuit currents exceed the permissible levels （40 kA in the 132 kV network and 63 kA in the 275 kV network） in some specific points. The examined measures include the a study on changing the neutral point policy, changing some lines from alternating current （AC） to direct current （DC）, dividing specific bus bars in some generating stations and applying current limiters. The paper also presents a new plan for the transmission network in order to manage the expected increase in short circuit levels in the future.展开更多
The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timi...The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.展开更多
中点钳位(neutral point clamped,NPC)型三电平逆变器并网工作环境恶劣,IGBT面临单管与双管同时故障的挑战,这使得故障特征之间的差异变得非常微弱,进而导致双管故障的识别精度难以有效提升。为此,提出了一种新的故障诊断方法,该方法结...中点钳位(neutral point clamped,NPC)型三电平逆变器并网工作环境恶劣,IGBT面临单管与双管同时故障的挑战,这使得故障特征之间的差异变得非常微弱,进而导致双管故障的识别精度难以有效提升。为此,提出了一种新的故障诊断方法,该方法结合了多通道的二维递归融合图和轻量化多尺度残差(lightweightmultiscale convolutional residuals,LMCR)网络。首先,通过仿真获取三相电流信号作为故障信号;再利用递归图(recurrence plot,RP)将三相电流信号分别转化为二维图并进行多通道融合,以捕捉时间序列中的周期性、突变点和趋势等特征;最后,将递归融合图作为输入,输入到LMCR模型中进行故障识别,LMCR模型整合多级Inception结构和残差网络,用于提取不同尺度的特征并融合这些特征,从而保证网络的梯度消失和爆炸。实验结果显示,该方法在IGBT故障识别中表现出色,无噪声环境下平均识别准确率达100%,噪声环境中也达到了92.53%,充分证明了该方法具有较强的特征提取能力和优异的抗噪性能。展开更多
由于开关器件故障是有源中性点箝位(active neutral point clamped,ANPC)三电平逆变器故障的主要类型,快速定位故障器件对提升ANPC三电平逆变器的可靠性具有重要意义。针对ANPC三电平逆变器开关器件开路故障,从传播路径的角度分析了不...由于开关器件故障是有源中性点箝位(active neutral point clamped,ANPC)三电平逆变器故障的主要类型,快速定位故障器件对提升ANPC三电平逆变器的可靠性具有重要意义。针对ANPC三电平逆变器开关器件开路故障,从传播路径的角度分析了不同调制算法下开关器件故障对输出电流的影响以及输出电流与负载侧电压的相位差对故障电流波形的影响。以三相输出电流作为故障特征量,提出一种基于切换调制策略的ANPC三电平逆变器开路故障诊断方法。首先采用电流平均值法先对故障开关器件的大致范围进行判定,然后切换调制策略以实现故障器件的精确定位。最后,通过仿真与实验验证了该方法可以在1个基波周期内实现故障定位,具有检测速度快、抗干扰能力强的优点,且无需额外增加用于故障检测的传感器。展开更多
本文提出了一种基于晶体管-晶体管逻辑(Transistor-Transistor Logic,TTL)协议的集成电路系统级测试系统,旨在解决复杂芯片测试中测试环境搭建及与分选机通讯的难题,同时满足市面上高端、特殊的集成电路测试专属化的需求。该系统由接口...本文提出了一种基于晶体管-晶体管逻辑(Transistor-Transistor Logic,TTL)协议的集成电路系统级测试系统,旨在解决复杂芯片测试中测试环境搭建及与分选机通讯的难题,同时满足市面上高端、特殊的集成电路测试专属化的需求。该系统由接口模块、电源模块、待测芯片连接模块、测试选择模块以及显示模块协同工作,实现了对多种集成电路的灵活测试,其工作流程为:①测试系统先向分选机发送开始测试信号,分选机将待测芯片从入料盘取出置入测试座中;②通过与测试系统通讯启动测试,测试系统对待测芯片进行测试并将测试结果发送至分选机端;③分选机根据测试系统反馈的结果将芯片放入不同的下料盘,完成芯片的良品与不良品分选。该集成电路系统级测试系统,突破了传统自动测试设备(Automatic Test Equipment,ATE)测试的限制,确保芯片在实际应用场景中与其他硬件、软件协同工作时的稳定性,显著提升了测试的灵活性与准确性。展开更多
文摘This paper describes the study analysis performed to evaluate the available and potential solutions to control the highly increasing short circuit （SC） levels in Kuwait power system. The real Kuwait High Voltage （HV） network was simulated to examine different measures at both 275 kV and 132 kV stations. The simulation results show that the short circuit currents exceed the permissible levels （40 kA in the 132 kV network and 63 kA in the 275 kV network） in some specific points. The examined measures include the a study on changing the neutral point policy, changing some lines from alternating current （AC） to direct current （DC）, dividing specific bus bars in some generating stations and applying current limiters. The paper also presents a new plan for the transmission network in order to manage the expected increase in short circuit levels in the future.
文摘The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.
文摘由于开关器件故障是有源中性点箝位(active neutral point clamped,ANPC)三电平逆变器故障的主要类型,快速定位故障器件对提升ANPC三电平逆变器的可靠性具有重要意义。针对ANPC三电平逆变器开关器件开路故障,从传播路径的角度分析了不同调制算法下开关器件故障对输出电流的影响以及输出电流与负载侧电压的相位差对故障电流波形的影响。以三相输出电流作为故障特征量,提出一种基于切换调制策略的ANPC三电平逆变器开路故障诊断方法。首先采用电流平均值法先对故障开关器件的大致范围进行判定,然后切换调制策略以实现故障器件的精确定位。最后,通过仿真与实验验证了该方法可以在1个基波周期内实现故障定位,具有检测速度快、抗干扰能力强的优点,且无需额外增加用于故障检测的传感器。
文摘本文提出了一种基于晶体管-晶体管逻辑(Transistor-Transistor Logic,TTL)协议的集成电路系统级测试系统,旨在解决复杂芯片测试中测试环境搭建及与分选机通讯的难题,同时满足市面上高端、特殊的集成电路测试专属化的需求。该系统由接口模块、电源模块、待测芯片连接模块、测试选择模块以及显示模块协同工作,实现了对多种集成电路的灵活测试,其工作流程为:①测试系统先向分选机发送开始测试信号,分选机将待测芯片从入料盘取出置入测试座中;②通过与测试系统通讯启动测试,测试系统对待测芯片进行测试并将测试结果发送至分选机端;③分选机根据测试系统反馈的结果将芯片放入不同的下料盘,完成芯片的良品与不良品分选。该集成电路系统级测试系统,突破了传统自动测试设备(Automatic Test Equipment,ATE)测试的限制,确保芯片在实际应用场景中与其他硬件、软件协同工作时的稳定性,显著提升了测试的灵活性与准确性。
