This paper describes the study analysis performed to evaluate the available and potential solutions to control the highly increasing short circuit （SC） levels in Kuwait power system. The real Kuwait High Voltage （H...This paper describes the study analysis performed to evaluate the available and potential solutions to control the highly increasing short circuit （SC） levels in Kuwait power system. The real Kuwait High Voltage （HV） network was simulated to examine different measures at both 275 kV and 132 kV stations. The simulation results show that the short circuit currents exceed the permissible levels （40 kA in the 132 kV network and 63 kA in the 275 kV network） in some specific points. The examined measures include the a study on changing the neutral point policy, changing some lines from alternating current （AC） to direct current （DC）, dividing specific bus bars in some generating stations and applying current limiters. The paper also presents a new plan for the transmission network in order to manage the expected increase in short circuit levels in the future.展开更多
The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timi...The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.展开更多
By employing the continuous parameter entangled state representations, we investigate the energy level and the wave function for a capacitively and mutual-inductively coupled LC mesoscopic circuit. It is found that in...By employing the continuous parameter entangled state representations, we investigate the energy level and the wave function for a capacitively and mutual-inductively coupled LC mesoscopic circuit. It is found that investigating the meso- scopic circuit in such representations can bring us the following conveniences. Firstly, the dynamical equation is naturally transformed into a single-variable differential equation. Second/y, the center-of-mass kinetic energy is included in the energy level of the system. Thus it is instructive to introduce the entangled state representation into the investigation of mesoscopic circuits.展开更多
A novel integrated circuit for driving LED lighting has been proposed, designed and fabricated. Besides the typical parts of LED driver, an integral part was added at the output terminal of error amplifier in the driv...A novel integrated circuit for driving LED lighting has been proposed, designed and fabricated. Besides the typical parts of LED driver, an integral part was added at the output terminal of error amplifier in the driver. In this way, a novel average current mode can be set up to take the place ordinary peak current control mode. In addition, a BUCK low-level topology was adopted, too. It can be used to drive up to eight 1 W HB LED lights with 350 mA constant current. In this way, the LED driver displays high performance, in which output current with less 1% error and total efficiency as high as 96%. The feasibility of the design has been verified by actual measurement on the fabricated chip.展开更多
Terahertz quantum cascade lasers（THz QCLs） emitted at 4.4 THz are fabricated and characterized. An equivalent circuit model is established based on the five-level rate equations to describe their characteristics. In...Terahertz quantum cascade lasers（THz QCLs） emitted at 4.4 THz are fabricated and characterized. An equivalent circuit model is established based on the five-level rate equations to describe their characteristics. In order to illustrate the capability of the model, the steady and dynamic performances of the fabricated THz QCLs are simulated by the model.Compared to the sophisticated numerical methods, the presented model has advantages of fast calculation and good compatibility with circuit simulation for system-level designs and optimizations. The validity of the model is verified by the experimental and numerical results.展开更多
In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity o...In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.展开更多
In order to obtain reasonable schemes of arrester in converter stations, the arrester scheme of "Xiluodu-Guangdong HVDC ± 500 kV double circuit transmission" project against lighting induced overvoltage...In order to obtain reasonable schemes of arrester in converter stations, the arrester scheme of "Xiluodu-Guangdong HVDC ± 500 kV double circuit transmission" project against lighting induced overvoltage, which was designed according to the main principle of lightning protection in converter station, is discussed. A calculation of the lighting induced overvoltage in Zhaotong converter station un- der various operation modes is performed with ATP-EMTP software, then the surge arrester configuration of the converter station is decided, and the arrester protection schemes of smoothing reactor and neutral line are studied. It is concluded that additional protection is necessary because of the relatively large gap between protected disconnecting switch and arrester of metallic return transfer bus. Plus, the smoothing reactor (SR) arrester near the valve hall could be removed to improve the scheme’s economic performance.展开更多
中点钳位(neutral point clamped,NPC)型三电平逆变器并网工作环境恶劣,IGBT面临单管与双管同时故障的挑战,这使得故障特征之间的差异变得非常微弱,进而导致双管故障的识别精度难以有效提升。为此,提出了一种新的故障诊断方法,该方法结...中点钳位(neutral point clamped,NPC)型三电平逆变器并网工作环境恶劣,IGBT面临单管与双管同时故障的挑战,这使得故障特征之间的差异变得非常微弱,进而导致双管故障的识别精度难以有效提升。为此,提出了一种新的故障诊断方法,该方法结合了多通道的二维递归融合图和轻量化多尺度残差(lightweightmultiscale convolutional residuals,LMCR)网络。首先,通过仿真获取三相电流信号作为故障信号;再利用递归图(recurrence plot,RP)将三相电流信号分别转化为二维图并进行多通道融合,以捕捉时间序列中的周期性、突变点和趋势等特征;最后,将递归融合图作为输入,输入到LMCR模型中进行故障识别,LMCR模型整合多级Inception结构和残差网络,用于提取不同尺度的特征并融合这些特征,从而保证网络的梯度消失和爆炸。实验结果显示,该方法在IGBT故障识别中表现出色,无噪声环境下平均识别准确率达100%,噪声环境中也达到了92.53%,充分证明了该方法具有较强的特征提取能力和优异的抗噪性能。展开更多
由于开关器件故障是有源中性点箝位(active neutral point clamped,ANPC)三电平逆变器故障的主要类型,快速定位故障器件对提升ANPC三电平逆变器的可靠性具有重要意义。针对ANPC三电平逆变器开关器件开路故障,从传播路径的角度分析了不...由于开关器件故障是有源中性点箝位(active neutral point clamped,ANPC)三电平逆变器故障的主要类型,快速定位故障器件对提升ANPC三电平逆变器的可靠性具有重要意义。针对ANPC三电平逆变器开关器件开路故障,从传播路径的角度分析了不同调制算法下开关器件故障对输出电流的影响以及输出电流与负载侧电压的相位差对故障电流波形的影响。以三相输出电流作为故障特征量,提出一种基于切换调制策略的ANPC三电平逆变器开路故障诊断方法。首先采用电流平均值法先对故障开关器件的大致范围进行判定,然后切换调制策略以实现故障器件的精确定位。最后,通过仿真与实验验证了该方法可以在1个基波周期内实现故障定位,具有检测速度快、抗干扰能力强的优点,且无需额外增加用于故障检测的传感器。展开更多
文摘This paper describes the study analysis performed to evaluate the available and potential solutions to control the highly increasing short circuit （SC） levels in Kuwait power system. The real Kuwait High Voltage （HV） network was simulated to examine different measures at both 275 kV and 132 kV stations. The simulation results show that the short circuit currents exceed the permissible levels （40 kA in the 132 kV network and 63 kA in the 275 kV network） in some specific points. The examined measures include the a study on changing the neutral point policy, changing some lines from alternating current （AC） to direct current （DC）, dividing specific bus bars in some generating stations and applying current limiters. The paper also presents a new plan for the transmission network in order to manage the expected increase in short circuit levels in the future.
文摘The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 11147009 and 11244005)the Natural Science Foundation of Shandong Province, China (Grant Nos. ZR2010AQ027 and ZR2012AM004)
文摘By employing the continuous parameter entangled state representations, we investigate the energy level and the wave function for a capacitively and mutual-inductively coupled LC mesoscopic circuit. It is found that investigating the meso- scopic circuit in such representations can bring us the following conveniences. Firstly, the dynamical equation is naturally transformed into a single-variable differential equation. Second/y, the center-of-mass kinetic energy is included in the energy level of the system. Thus it is instructive to introduce the entangled state representation into the investigation of mesoscopic circuits.
文摘A novel integrated circuit for driving LED lighting has been proposed, designed and fabricated. Besides the typical parts of LED driver, an integral part was added at the output terminal of error amplifier in the driver. In this way, a novel average current mode can be set up to take the place ordinary peak current control mode. In addition, a BUCK low-level topology was adopted, too. It can be used to drive up to eight 1 W HB LED lights with 350 mA constant current. In this way, the LED driver displays high performance, in which output current with less 1% error and total efficiency as high as 96%. The feasibility of the design has been verified by actual measurement on the fabricated chip.
基金Project supported by the National Basic Research Program of China(Grant No.2014CB339803)the National High Technology Research and Development Program of China(Grant No.2011AA010205)+5 种基金the National Natural Science Foundation of China(Grant Nos.61131006,61321492,and 61404149)the Major National Development Project of Scientific Instrument and Equipment,China(Grant No.2011YQ150021)the National Science and Technology Major Project,China(Grant No.2011ZX02707)the Major Project,China(Grant No.YYYJ-1123-1)the International Collaboration and Innovation Program on High Mobility Materials Engineering of the Chinese Academy of Sciencesthe Shanghai Municipal Commission of Science and Technology,China(Grant Nos.14530711300)
文摘Terahertz quantum cascade lasers（THz QCLs） emitted at 4.4 THz are fabricated and characterized. An equivalent circuit model is established based on the five-level rate equations to describe their characteristics. In order to illustrate the capability of the model, the steady and dynamic performances of the fabricated THz QCLs are simulated by the model.Compared to the sophisticated numerical methods, the presented model has advantages of fast calculation and good compatibility with circuit simulation for system-level designs and optimizations. The validity of the model is verified by the experimental and numerical results.
基金supported by the National High Technology Research and Development Program of China (863 Program) (2002AA1Z1490)Specialized Research Fund for the Doctoral Program of Higher Education (20040486049)the University Cooperative Research Fund of Huawei Technology Co., Ltd
文摘In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.
基金Project supported by Key Project of National Natural Science Foundation of China （50737003）.
文摘In order to obtain reasonable schemes of arrester in converter stations, the arrester scheme of "Xiluodu-Guangdong HVDC ± 500 kV double circuit transmission" project against lighting induced overvoltage, which was designed according to the main principle of lightning protection in converter station, is discussed. A calculation of the lighting induced overvoltage in Zhaotong converter station un- der various operation modes is performed with ATP-EMTP software, then the surge arrester configuration of the converter station is decided, and the arrester protection schemes of smoothing reactor and neutral line are studied. It is concluded that additional protection is necessary because of the relatively large gap between protected disconnecting switch and arrester of metallic return transfer bus. Plus, the smoothing reactor (SR) arrester near the valve hall could be removed to improve the scheme’s economic performance.
文摘由于开关器件故障是有源中性点箝位(active neutral point clamped,ANPC)三电平逆变器故障的主要类型,快速定位故障器件对提升ANPC三电平逆变器的可靠性具有重要意义。针对ANPC三电平逆变器开关器件开路故障,从传播路径的角度分析了不同调制算法下开关器件故障对输出电流的影响以及输出电流与负载侧电压的相位差对故障电流波形的影响。以三相输出电流作为故障特征量,提出一种基于切换调制策略的ANPC三电平逆变器开路故障诊断方法。首先采用电流平均值法先对故障开关器件的大致范围进行判定,然后切换调制策略以实现故障器件的精确定位。最后,通过仿真与实验验证了该方法可以在1个基波周期内实现故障定位,具有检测速度快、抗干扰能力强的优点,且无需额外增加用于故障检测的传感器。
