Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swi...Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-am and 90-nm complementary metal-oxide semiconductor （CMOS） interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.展开更多
This paper proposes third order tunable bandwidth active Switched-Capacitor filter. The circuit consists of only op-amps and switched capacitors. The circuit is designed for circuit merit factor Q = 10. The proposed c...This paper proposes third order tunable bandwidth active Switched-Capacitor filter. The circuit consists of only op-amps and switched capacitors. The circuit is designed for circuit merit factor Q = 10. The proposed circuit implements three filter functions low pass, band pass and high pass simultaneously in single circuit. The filter circuit can be used for both narrow as well as for wide bandwidth. For various values of cut-off frequencies the behaviour of circuit is studied. The circuit works properly only for higher central frequencies, when f0 > 10 kHz.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005)
文摘Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-am and 90-nm complementary metal-oxide semiconductor （CMOS） interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.
文摘This paper proposes third order tunable bandwidth active Switched-Capacitor filter. The circuit consists of only op-amps and switched capacitors. The circuit is designed for circuit merit factor Q = 10. The proposed circuit implements three filter functions low pass, band pass and high pass simultaneously in single circuit. The filter circuit can be used for both narrow as well as for wide bandwidth. For various values of cut-off frequencies the behaviour of circuit is studied. The circuit works properly only for higher central frequencies, when f0 > 10 kHz.
