Motivation.As artificial intelligence(AI)workloads escalate exponentially,ultra-thin,high-efficiency voltage regulator modules(VRMs)with exceptional power density become essential for backside-mounted configurations[1...Motivation.As artificial intelligence(AI)workloads escalate exponentially,ultra-thin,high-efficiency voltage regulator modules(VRMs)with exceptional power density become essential for backside-mounted configurations[1].Thus,highdensity multiphase DC−DC converters are pivotal for implementing vertical power delivery(VPD)architectures in XPU platforms.Strategically positioning these converters beneath processors and maximizing spatial utilization enables core rail currents exceeding 2 kA while significantly reducing the power distribution network(PDN)losses compared to conventional solutions.The VPD configuration elevates system-level energy efficiency with>100 W power saving per processor,yielding megawatt-scale savings in a datacenter that uses~100000 processors.The synergy of 48 V power conversion architectures and advanced packaging techniques enables the industry’s commitment to balancing computational demands with CO_(2)emission reduction and environmental sustainability.展开更多
Multi-organ-on-a-chip(MOOC)technology represents a pivotal direction in the organ-on-a-chip field,seeking to emulate the complex interactions of multiple human organs in vitro through microfluidic systems.This technol...Multi-organ-on-a-chip(MOOC)technology represents a pivotal direction in the organ-on-a-chip field,seeking to emulate the complex interactions of multiple human organs in vitro through microfluidic systems.This technology overcomes the limitations of traditional single-organ models,providing a novel platform for investigating complex disease mechanisms and evaluating drug efficacy and toxicity.Although it demonstrates broad application prospects,its development still faces critical bottlenecks,including inadequate physiological coupling between organs,short functional maintenance durations,and limited real-time monitoring capabilities.Contemporary research is advancing along three key directions,including functional coupling,sensor integration,and full-process automation systems,to propel the technology toward enhanced levels of physiological relevance and predictive accuracy.展开更多
This paper presents the design of a full-duplex multi-rate vocoder which implements an LPC-10, CELPC and VSELPC algorithms in real time. A single commercially available digital signal processor IC, the TMS320C25, is u...This paper presents the design of a full-duplex multi-rate vocoder which implements an LPC-10, CELPC and VSELPC algorithms in real time. A single commercially available digital signal processor IC, the TMS320C25, is used to perform the digital processing. The channel interfaces are configured with the design of ASIC, and including timing and control logic circuits.展开更多
A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time geneti...A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.展开更多
欧司朗光电半导体推出的RGB Multi Chip LED,被应用于FormoLight显示器上。其紧凑的外形设计,使得它们在不同大小体积的LED视频显示器上可以显示特殊的图像格式。该显示器区别于液晶显示器,LED不再作为人们看不到的背光光源，在这种应...欧司朗光电半导体推出的RGB Multi Chip LED,被应用于FormoLight显示器上。其紧凑的外形设计,使得它们在不同大小体积的LED视频显示器上可以显示特殊的图像格式。该显示器区别于液晶显示器,LED不再作为人们看不到的背光光源，在这种应用上，LED在显示器的表面清晰可见。展开更多
This paper considers blind chip rate estimation of DS-SS signals in multi-rate and multi-user DS-CDMA systems over channels having slow flat Rayleigh fading plus additive white Gaussian noise. Channel impulse response...This paper considers blind chip rate estimation of DS-SS signals in multi-rate and multi-user DS-CDMA systems over channels having slow flat Rayleigh fading plus additive white Gaussian noise. Channel impulse response is estimated by a subspace method, and then the chip rate of each signal is estimated using zero crossing of estimated differential channel impulse response. For chip rate estimation of each user, an algorithm which uses weighted zero-crossing ratio is proposed. Maximum value of the weighted zero crossing ratio takes place in the Nyquist rate sampling frequency, which equals to the twice of the chip rate. Furthermore, bit time of each user is estimated using fluctuations of autocorrelation estimators. Since code length of each user can be obtained using bit time and chip time ratio. Fading channels reduce reliability factor of the proposed algo-rithm. To overcome this problem, a receiver with multiple antennas is proposed, and the reliability factor of the proposed algorithm is analyzed over both spatially correlated and independent fading channels.展开更多
针对水下无人航行器(underwater unmanned vehicle,UUV)主动声呐系统对信号处理实时性、能效比及集成度的需求,采用模块化设计以及软硬件协同设计思想,提出一种基于异构多处理器片上系统(multi-processor system on chip,MPSoC)的主动...针对水下无人航行器(underwater unmanned vehicle,UUV)主动声呐系统对信号处理实时性、能效比及集成度的需求,采用模块化设计以及软硬件协同设计思想,提出一种基于异构多处理器片上系统(multi-processor system on chip,MPSoC)的主动声呐实时信号处理算法的加速方案。首先研究适合边缘端部署的声呐信号处理算法;然后设计基于MPSoC的加速计算结构,将数字下变频、逆/快速傅里叶变换、波束形成等具有高计算复杂性的处理步骤移植到可编程逻辑端,实现显著加速;最后将目标检测等复杂度较低的步骤部署在处理器系统端,实现更高的灵活性。仿真及湖上试验结果表明,提出的方案可在数据更新周期的41%时间内完成1帧回波数据的实时处理,并可在复杂水下环境下实时有效探测运动目标。该方案在水下UUV主动声呐探测领域具有广阔的应用前景。展开更多
传统多芯片组件封装技术是高密度电子封装技术中的代表性技术,但是受封装内微波信号传输的制约,其射频微波芯片采取水平化的排布方式,难以满足高频率、高密度的射频微波系统级封装需求。随着基板材料技术和叠层工艺不断进步发展,并逐渐...传统多芯片组件封装技术是高密度电子封装技术中的代表性技术,但是受封装内微波信号传输的制约,其射频微波芯片采取水平化的排布方式,难以满足高频率、高密度的射频微波系统级封装需求。随着基板材料技术和叠层工艺不断进步发展,并逐渐应用至射频微波领域,利用晶圆级、三维化和异构集成等实现微波封装集成,使得射频微波组件系统级封装(system in package,SiP)技术成为后摩尔时代增加系统集成度、实现产品小型化的最有效方案之一。文章概述了微波SiP的概念、特点,以及其架构分类。介绍了微波SiP应用材料的发展及应用于微波收发通道的最新研究进展和存在的挑战,展望了未来发展趋势,对其在航天领域的应用发展指明了方向。展开更多
To enhance the computational density and energy efficiency of on-chip neuromorphic hardware,this study introduces a novel network architecture for multi-task processing with in-memory optical computing.On-chip optical...To enhance the computational density and energy efficiency of on-chip neuromorphic hardware,this study introduces a novel network architecture for multi-task processing with in-memory optical computing.On-chip optical neural networks are celebrated for their capability to transduce a substantial volume of parameters into optical form while conducting passive computing,yet they encounter challenges in scalability and multitasking.Leveraging the principles of transfer learning,this approach involves embedding the majority of parameters into fixed optical components and a minority into adjustable electrical components.Furthermore,with deep regression algorithm in modeling physical propagation process,a compact optical neural network achieve to handle diverse tasks.In this work,two ultra-compact in-memory diffraction-based chips with integration of more than 60,000 parameters/mm^(2) were fabricated,employing deep neural network model and the hard parameter sharing algorithm,to perform multifaceted classification and regression tasks,respectively.The experimental results demonstrate that these chips achieve accuracies comparable to those of electrical networks while significantly reducing the power-intensive digital computation by 90%.Our work heralds strong potential for advancing in-memory optical computing frameworks and next generation of artificial intelligence platforms.展开更多
文摘Motivation.As artificial intelligence(AI)workloads escalate exponentially,ultra-thin,high-efficiency voltage regulator modules(VRMs)with exceptional power density become essential for backside-mounted configurations[1].Thus,highdensity multiphase DC−DC converters are pivotal for implementing vertical power delivery(VPD)architectures in XPU platforms.Strategically positioning these converters beneath processors and maximizing spatial utilization enables core rail currents exceeding 2 kA while significantly reducing the power distribution network(PDN)losses compared to conventional solutions.The VPD configuration elevates system-level energy efficiency with>100 W power saving per processor,yielding megawatt-scale savings in a datacenter that uses~100000 processors.The synergy of 48 V power conversion architectures and advanced packaging techniques enables the industry’s commitment to balancing computational demands with CO_(2)emission reduction and environmental sustainability.
基金supported by the Shenzhen Medical Research Fund(Grant No.A2303049)Guangdong Basic and Applied Basic Research(Grant No.2023A1515010647)+1 种基金National Natural Science Foundation of China(Grant No.22004135)Shenzhen Science and Technology Program(Grant No.RCBS20210706092409020,GXWD20201231165807008,20200824162253002).
文摘Multi-organ-on-a-chip(MOOC)technology represents a pivotal direction in the organ-on-a-chip field,seeking to emulate the complex interactions of multiple human organs in vitro through microfluidic systems.This technology overcomes the limitations of traditional single-organ models,providing a novel platform for investigating complex disease mechanisms and evaluating drug efficacy and toxicity.Although it demonstrates broad application prospects,its development still faces critical bottlenecks,including inadequate physiological coupling between organs,short functional maintenance durations,and limited real-time monitoring capabilities.Contemporary research is advancing along three key directions,including functional coupling,sensor integration,and full-process automation systems,to propel the technology toward enhanced levels of physiological relevance and predictive accuracy.
文摘This paper presents the design of a full-duplex multi-rate vocoder which implements an LPC-10, CELPC and VSELPC algorithms in real time. A single commercially available digital signal processor IC, the TMS320C25, is used to perform the digital processing. The channel interfaces are configured with the design of ASIC, and including timing and control logic circuits.
文摘A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.
文摘This paper considers blind chip rate estimation of DS-SS signals in multi-rate and multi-user DS-CDMA systems over channels having slow flat Rayleigh fading plus additive white Gaussian noise. Channel impulse response is estimated by a subspace method, and then the chip rate of each signal is estimated using zero crossing of estimated differential channel impulse response. For chip rate estimation of each user, an algorithm which uses weighted zero-crossing ratio is proposed. Maximum value of the weighted zero crossing ratio takes place in the Nyquist rate sampling frequency, which equals to the twice of the chip rate. Furthermore, bit time of each user is estimated using fluctuations of autocorrelation estimators. Since code length of each user can be obtained using bit time and chip time ratio. Fading channels reduce reliability factor of the proposed algo-rithm. To overcome this problem, a receiver with multiple antennas is proposed, and the reliability factor of the proposed algorithm is analyzed over both spatially correlated and independent fading channels.
文摘针对水下无人航行器(underwater unmanned vehicle,UUV)主动声呐系统对信号处理实时性、能效比及集成度的需求,采用模块化设计以及软硬件协同设计思想,提出一种基于异构多处理器片上系统(multi-processor system on chip,MPSoC)的主动声呐实时信号处理算法的加速方案。首先研究适合边缘端部署的声呐信号处理算法;然后设计基于MPSoC的加速计算结构,将数字下变频、逆/快速傅里叶变换、波束形成等具有高计算复杂性的处理步骤移植到可编程逻辑端,实现显著加速;最后将目标检测等复杂度较低的步骤部署在处理器系统端,实现更高的灵活性。仿真及湖上试验结果表明,提出的方案可在数据更新周期的41%时间内完成1帧回波数据的实时处理,并可在复杂水下环境下实时有效探测运动目标。该方案在水下UUV主动声呐探测领域具有广阔的应用前景。
文摘传统多芯片组件封装技术是高密度电子封装技术中的代表性技术,但是受封装内微波信号传输的制约,其射频微波芯片采取水平化的排布方式,难以满足高频率、高密度的射频微波系统级封装需求。随着基板材料技术和叠层工艺不断进步发展,并逐渐应用至射频微波领域,利用晶圆级、三维化和异构集成等实现微波封装集成,使得射频微波组件系统级封装(system in package,SiP)技术成为后摩尔时代增加系统集成度、实现产品小型化的最有效方案之一。文章概述了微波SiP的概念、特点,以及其架构分类。介绍了微波SiP应用材料的发展及应用于微波收发通道的最新研究进展和存在的挑战,展望了未来发展趋势,对其在航天领域的应用发展指明了方向。
基金supported by the National Key R&D Plan of China(2024YFE0203600)the National Natural Science Foundation of China(62135009).
文摘To enhance the computational density and energy efficiency of on-chip neuromorphic hardware,this study introduces a novel network architecture for multi-task processing with in-memory optical computing.On-chip optical neural networks are celebrated for their capability to transduce a substantial volume of parameters into optical form while conducting passive computing,yet they encounter challenges in scalability and multitasking.Leveraging the principles of transfer learning,this approach involves embedding the majority of parameters into fixed optical components and a minority into adjustable electrical components.Furthermore,with deep regression algorithm in modeling physical propagation process,a compact optical neural network achieve to handle diverse tasks.In this work,two ultra-compact in-memory diffraction-based chips with integration of more than 60,000 parameters/mm^(2) were fabricated,employing deep neural network model and the hard parameter sharing algorithm,to perform multifaceted classification and regression tasks,respectively.The experimental results demonstrate that these chips achieve accuracies comparable to those of electrical networks while significantly reducing the power-intensive digital computation by 90%.Our work heralds strong potential for advancing in-memory optical computing frameworks and next generation of artificial intelligence platforms.
