Multi-organ-on-a-chip(MOOC)technology represents a pivotal direction in the organ-on-a-chip field,seeking to emulate the complex interactions of multiple human organs in vitro through microfluidic systems.This technol...Multi-organ-on-a-chip(MOOC)technology represents a pivotal direction in the organ-on-a-chip field,seeking to emulate the complex interactions of multiple human organs in vitro through microfluidic systems.This technology overcomes the limitations of traditional single-organ models,providing a novel platform for investigating complex disease mechanisms and evaluating drug efficacy and toxicity.Although it demonstrates broad application prospects,its development still faces critical bottlenecks,including inadequate physiological coupling between organs,short functional maintenance durations,and limited real-time monitoring capabilities.Contemporary research is advancing along three key directions,including functional coupling,sensor integration,and full-process automation systems,to propel the technology toward enhanced levels of physiological relevance and predictive accuracy.展开更多
Motivation.As artificial intelligence(AI)workloads escalate exponentially,ultra-thin,high-efficiency voltage regulator modules(VRMs)with exceptional power density become essential for backside-mounted configurations[1...Motivation.As artificial intelligence(AI)workloads escalate exponentially,ultra-thin,high-efficiency voltage regulator modules(VRMs)with exceptional power density become essential for backside-mounted configurations[1].Thus,highdensity multiphase DC−DC converters are pivotal for implementing vertical power delivery(VPD)architectures in XPU platforms.Strategically positioning these converters beneath processors and maximizing spatial utilization enables core rail currents exceeding 2 kA while significantly reducing the power distribution network(PDN)losses compared to conventional solutions.The VPD configuration elevates system-level energy efficiency with>100 W power saving per processor,yielding megawatt-scale savings in a datacenter that uses~100000 processors.The synergy of 48 V power conversion architectures and advanced packaging techniques enables the industry’s commitment to balancing computational demands with CO_(2)emission reduction and environmental sustainability.展开更多
This paper presents the design of a full-duplex multi-rate vocoder which implements an LPC-10, CELPC and VSELPC algorithms in real time. A single commercially available digital signal processor IC, the TMS320C25, is u...This paper presents the design of a full-duplex multi-rate vocoder which implements an LPC-10, CELPC and VSELPC algorithms in real time. A single commercially available digital signal processor IC, the TMS320C25, is used to perform the digital processing. The channel interfaces are configured with the design of ASIC, and including timing and control logic circuits.展开更多
A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time geneti...A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.展开更多
欧司朗光电半导体推出的RGB Multi Chip LED,被应用于FormoLight显示器上。其紧凑的外形设计,使得它们在不同大小体积的LED视频显示器上可以显示特殊的图像格式。该显示器区别于液晶显示器,LED不再作为人们看不到的背光光源，在这种应...欧司朗光电半导体推出的RGB Multi Chip LED,被应用于FormoLight显示器上。其紧凑的外形设计,使得它们在不同大小体积的LED视频显示器上可以显示特殊的图像格式。该显示器区别于液晶显示器,LED不再作为人们看不到的背光光源，在这种应用上，LED在显示器的表面清晰可见。展开更多
This paper considers blind chip rate estimation of DS-SS signals in multi-rate and multi-user DS-CDMA systems over channels having slow flat Rayleigh fading plus additive white Gaussian noise. Channel impulse response...This paper considers blind chip rate estimation of DS-SS signals in multi-rate and multi-user DS-CDMA systems over channels having slow flat Rayleigh fading plus additive white Gaussian noise. Channel impulse response is estimated by a subspace method, and then the chip rate of each signal is estimated using zero crossing of estimated differential channel impulse response. For chip rate estimation of each user, an algorithm which uses weighted zero-crossing ratio is proposed. Maximum value of the weighted zero crossing ratio takes place in the Nyquist rate sampling frequency, which equals to the twice of the chip rate. Furthermore, bit time of each user is estimated using fluctuations of autocorrelation estimators. Since code length of each user can be obtained using bit time and chip time ratio. Fading channels reduce reliability factor of the proposed algo-rithm. To overcome this problem, a receiver with multiple antennas is proposed, and the reliability factor of the proposed algorithm is analyzed over both spatially correlated and independent fading channels.展开更多
目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频...目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频率调节(Dynamic Voltage Frequency Scaling,DVFS)技术,研究异构多核实时系统中基于任务同步的节能调度问题,提出同步感知的最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First,SA-LESF)。该算法针对所有任务的速度配置进行迭代优化,直至所有任务均达到其最大限度节能的速度配置。此外,进一步提出基于动态松弛时间回收的同步感知最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First with Dynamic Reclamation,SA-LESF-DR)。该算法在保证实时任务可调度的同时,实施相应的回收策略,进一步降低系统能耗。实验结果表明,SA-LESF与SA-LESF-DR算法在能耗表现上具有优势,在相同任务集下,相比其他算法可节省高达30%的能耗。展开更多
A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC...A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.展开更多
There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable...There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.展开更多
The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power...The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.展开更多
基金supported by the Shenzhen Medical Research Fund(Grant No.A2303049)Guangdong Basic and Applied Basic Research(Grant No.2023A1515010647)+1 种基金National Natural Science Foundation of China(Grant No.22004135)Shenzhen Science and Technology Program(Grant No.RCBS20210706092409020,GXWD20201231165807008,20200824162253002).
文摘Multi-organ-on-a-chip(MOOC)technology represents a pivotal direction in the organ-on-a-chip field,seeking to emulate the complex interactions of multiple human organs in vitro through microfluidic systems.This technology overcomes the limitations of traditional single-organ models,providing a novel platform for investigating complex disease mechanisms and evaluating drug efficacy and toxicity.Although it demonstrates broad application prospects,its development still faces critical bottlenecks,including inadequate physiological coupling between organs,short functional maintenance durations,and limited real-time monitoring capabilities.Contemporary research is advancing along three key directions,including functional coupling,sensor integration,and full-process automation systems,to propel the technology toward enhanced levels of physiological relevance and predictive accuracy.
文摘Motivation.As artificial intelligence(AI)workloads escalate exponentially,ultra-thin,high-efficiency voltage regulator modules(VRMs)with exceptional power density become essential for backside-mounted configurations[1].Thus,highdensity multiphase DC−DC converters are pivotal for implementing vertical power delivery(VPD)architectures in XPU platforms.Strategically positioning these converters beneath processors and maximizing spatial utilization enables core rail currents exceeding 2 kA while significantly reducing the power distribution network(PDN)losses compared to conventional solutions.The VPD configuration elevates system-level energy efficiency with>100 W power saving per processor,yielding megawatt-scale savings in a datacenter that uses~100000 processors.The synergy of 48 V power conversion architectures and advanced packaging techniques enables the industry’s commitment to balancing computational demands with CO_(2)emission reduction and environmental sustainability.
文摘This paper presents the design of a full-duplex multi-rate vocoder which implements an LPC-10, CELPC and VSELPC algorithms in real time. A single commercially available digital signal processor IC, the TMS320C25, is used to perform the digital processing. The channel interfaces are configured with the design of ASIC, and including timing and control logic circuits.
文摘A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.
文摘This paper considers blind chip rate estimation of DS-SS signals in multi-rate and multi-user DS-CDMA systems over channels having slow flat Rayleigh fading plus additive white Gaussian noise. Channel impulse response is estimated by a subspace method, and then the chip rate of each signal is estimated using zero crossing of estimated differential channel impulse response. For chip rate estimation of each user, an algorithm which uses weighted zero-crossing ratio is proposed. Maximum value of the weighted zero crossing ratio takes place in the Nyquist rate sampling frequency, which equals to the twice of the chip rate. Furthermore, bit time of each user is estimated using fluctuations of autocorrelation estimators. Since code length of each user can be obtained using bit time and chip time ratio. Fading channels reduce reliability factor of the proposed algo-rithm. To overcome this problem, a receiver with multiple antennas is proposed, and the reliability factor of the proposed algorithm is analyzed over both spatially correlated and independent fading channels.
文摘目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频率调节(Dynamic Voltage Frequency Scaling,DVFS)技术,研究异构多核实时系统中基于任务同步的节能调度问题,提出同步感知的最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First,SA-LESF)。该算法针对所有任务的速度配置进行迭代优化,直至所有任务均达到其最大限度节能的速度配置。此外,进一步提出基于动态松弛时间回收的同步感知最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First with Dynamic Reclamation,SA-LESF-DR)。该算法在保证实时任务可调度的同时,实施相应的回收策略,进一步降低系统能耗。实验结果表明,SA-LESF与SA-LESF-DR算法在能耗表现上具有优势,在相同任务集下,相比其他算法可节省高达30%的能耗。
基金Supported by the Ministerial Level Advanced Research Foundation (SP240012)
文摘A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.
基金Supported by the Guangzhou Key Technology R&D Program (No.2007Z2-D0011)
文摘There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.
基金supported in part by the National Natural Science Foundation of China(No.61306027)
文摘The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.
