in this paper, a turbo Iterstive receiver structure with chip equalization is proposed for the 3G high-speed downllnk packet access （HSDPA） systems. The receiver equalizes the channel prior to the dlspreadlng and th...in this paper, a turbo Iterstive receiver structure with chip equalization is proposed for the 3G high-speed downllnk packet access （HSDPA） systems. The receiver equalizes the channel prior to the dlspreadlng and then performs two successive soft-output decisions, achieved by s soft-Input soft-output （SISO） multi-code detector and a SISO turbo decoder through an Iteratlve process. At each Iteration, extrinsic information Is extracted from detection and decoding stages and Is then used as a priori Information In the next Iteration, Just as In turbo decoding. Computer simulations show that the turbo Iterstlve receiver structure with chip equsllzation offers significant performance gain over the traditional receiver structure.展开更多
基金Supported by the National Natural Science Foundation of China (Grant No. 60496311)Program for New Century Excellent Talents in Uni-versity
文摘in this paper, a turbo Iterstive receiver structure with chip equalization is proposed for the 3G high-speed downllnk packet access （HSDPA） systems. The receiver equalizes the channel prior to the dlspreadlng and then performs two successive soft-output decisions, achieved by s soft-Input soft-output （SISO） multi-code detector and a SISO turbo decoder through an Iteratlve process. At each Iteration, extrinsic information Is extracted from detection and decoding stages and Is then used as a priori Information In the next Iteration, Just as In turbo decoding. Computer simulations show that the turbo Iterstlve receiver structure with chip equsllzation offers significant performance gain over the traditional receiver structure.
