Because of the limitations of electric vehicle(EV)battery technology and relevant supporting facilities,there is a great risk of breakdown of EVs during driving.The resulting driver“range anxiety”greatly affects the...Because of the limitations of electric vehicle(EV)battery technology and relevant supporting facilities,there is a great risk of breakdown of EVs during driving.The resulting driver“range anxiety”greatly affects the travel quality of EVs.These limitations should be overcome to promote the use of EVs.In this study,a method for travel path planning considering EV power supply was developed.First,based on real-time road conditions,a dynamic energy model of EVs was established considering the driving energy and accessory energy.Second,a multi-objective travel path planning model of EVs was constructed considering the power supply,taking the distance,time,energy,and charging cost as the optimization objectives.Finally,taking the actual traffic network of 15 km×15 km area in a city as the research object,the model was simulated and verified in MATLAB based on Dijkstra shortest path algorithm.The simulation results show that compared with the traditional route planning method,the total distance in the proposed optimal route planning method increased by 1.18%,but the energy consumption,charging cost,and driving time decreased by 11.62%,41.26%and 11.00%,respectively,thus effectively reducing the travel cost of EVs and improving the driving quality of EVs.展开更多
A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is signif...A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Subject to specified power con- sumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator （VCO）, CP and phase/frequency detector （PFD） in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal （MOM） capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.展开更多
基金Projects(51908388,51508315,51905320)supported by the National Natural Science Foundation of ChinaProject(2019 JZZY 010911)supported by the Key R&D Program of Shandong Province,China+1 种基金Project supported by the Shandong University of Technology&Zibo City Integration Develo pment Project,ChinaProject(ZR 2021 MG 012)supported by Shandong Provincial Natural Science Foundation,China。
文摘Because of the limitations of electric vehicle(EV)battery technology and relevant supporting facilities,there is a great risk of breakdown of EVs during driving.The resulting driver“range anxiety”greatly affects the travel quality of EVs.These limitations should be overcome to promote the use of EVs.In this study,a method for travel path planning considering EV power supply was developed.First,based on real-time road conditions,a dynamic energy model of EVs was established considering the driving energy and accessory energy.Second,a multi-objective travel path planning model of EVs was constructed considering the power supply,taking the distance,time,energy,and charging cost as the optimization objectives.Finally,taking the actual traffic network of 15 km×15 km area in a city as the research object,the model was simulated and verified in MATLAB based on Dijkstra shortest path algorithm.The simulation results show that compared with the traditional route planning method,the total distance in the proposed optimal route planning method increased by 1.18%,but the energy consumption,charging cost,and driving time decreased by 11.62%,41.26%and 11.00%,respectively,thus effectively reducing the travel cost of EVs and improving the driving quality of EVs.
基金Project supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033)the National High-Tech Program of China(No.2013AA014103)
文摘A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Subject to specified power con- sumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator （VCO）, CP and phase/frequency detector （PFD） in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal （MOM） capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.
