An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasit...An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.展开更多
We propose a modular multilevel converter(MMC)based three-phase four-wire(3P4W)split capacitor distribution static synchronous compensator(DSTATCOM),aiming at compensating unbalanced and reactive load currents.Due to ...We propose a modular multilevel converter(MMC)based three-phase four-wire(3P4W)split capacitor distribution static synchronous compensator(DSTATCOM),aiming at compensating unbalanced and reactive load currents.Due to the zero-sequence current compensation,the circulating current char-acteristics of 3P4W MMC-DSTATCOM are different from conventional MMCs.Moreover,the distinct working principle of IMMC would affect the features of split capacitor voltage.The decoupled positive-,negative-and zero-sequence second-order and DC components of the circulating current are deduced explicitly.Two proportional-integral controllers with dual dq transformation are employed to suppress the positive-and negative-sequence components of second-order circulating current,while quasi proportional-resonance controller is designed to eliminate the zero-sequence component.Besides,the phenomenon of the unbalanced split capacitor voltages is revealed,and fast-tracking balancing method by controlling zero-sequence current flowing through the split capacitors is provided.Digital simulation results verify the accuracy of the analysis and the feasibility of the suppression methods.展开更多
This paper presents a low power 10 bit 300 ksps successive approximation register analog-to-digital converter （SAR ADC） which is applied in wireless sensor network （WSN） applications. A single ended energy- saving...This paper presents a low power 10 bit 300 ksps successive approximation register analog-to-digital converter （SAR ADC） which is applied in wireless sensor network （WSN） applications. A single ended energy- saving split capacitor DAC array and a latch comparator with a rail to rail input stage are utilized to implement the ADC, which can reduce power dissipation while expanding the full scale input range and improve the signal-to- noise ratio （SNR）. For power optimization the supply voltage of the SAR ADC is designed to be as low as 2 V. Four analog input channels are designed which make the ADC more suitable for WSN applications. The prototype circuit is fabricated using 3.3 V, 0.35μm 2P4M CMOS technology and occupies an active chip area of 1.23 mm2. The test results show that the power dissipation is only 200μW at a 2 V power supply and a sampling rate of 166 ksps. The calculated SNR is 58.25 dB, the ENOB is 9.38 bit and the FOM is 4.95 p J/conversion-step.展开更多
基金Supported by National Science and Technology Major Project of China(No.2012ZX03004008)
文摘An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.
基金This work was supported in part by the National Natural Science Foundation of China(No.51807073).
文摘We propose a modular multilevel converter(MMC)based three-phase four-wire(3P4W)split capacitor distribution static synchronous compensator(DSTATCOM),aiming at compensating unbalanced and reactive load currents.Due to the zero-sequence current compensation,the circulating current char-acteristics of 3P4W MMC-DSTATCOM are different from conventional MMCs.Moreover,the distinct working principle of IMMC would affect the features of split capacitor voltage.The decoupled positive-,negative-and zero-sequence second-order and DC components of the circulating current are deduced explicitly.Two proportional-integral controllers with dual dq transformation are employed to suppress the positive-and negative-sequence components of second-order circulating current,while quasi proportional-resonance controller is designed to eliminate the zero-sequence component.Besides,the phenomenon of the unbalanced split capacitor voltages is revealed,and fast-tracking balancing method by controlling zero-sequence current flowing through the split capacitors is provided.Digital simulation results verify the accuracy of the analysis and the feasibility of the suppression methods.
基金supported by the National Natural Science Foundation of China(No.61107025)the Key Innovation Team Project of Zhejiang Province(No.2010R50010)
文摘This paper presents a low power 10 bit 300 ksps successive approximation register analog-to-digital converter （SAR ADC） which is applied in wireless sensor network （WSN） applications. A single ended energy- saving split capacitor DAC array and a latch comparator with a rail to rail input stage are utilized to implement the ADC, which can reduce power dissipation while expanding the full scale input range and improve the signal-to- noise ratio （SNR）. For power optimization the supply voltage of the SAR ADC is designed to be as low as 2 V. Four analog input channels are designed which make the ADC more suitable for WSN applications. The prototype circuit is fabricated using 3.3 V, 0.35μm 2P4M CMOS technology and occupies an active chip area of 1.23 mm2. The test results show that the power dissipation is only 200μW at a 2 V power supply and a sampling rate of 166 ksps. The calculated SNR is 58.25 dB, the ENOB is 9.38 bit and the FOM is 4.95 p J/conversion-step.
