A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, w...A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.展开更多
A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sa...A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.展开更多
A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed.This structure is based on associating two sets of two capacitors in cross series during the amplificat...A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed.This structure is based on associating two sets of two capacitors in cross series during the amplification phase.This circuit permits the common-mode voltage of the sample signal to reach full swing.Using the charge-complement technique,the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively.Simulation results show that as sample signal common-mode voltage changes,the difference between the minimum and maximum gain error is less than 0.03%.When the capacitor mismatch is increased from 0 to 0.2%,the gain error is deteriorated by 0.00015%）.In all simulations,the gain of amplifier is 69 dB.展开更多
A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to e...A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.展开更多
支路传输功率、节点电压等的越限是制约系统输电能力提高的重要因素,为此文章采用连续潮流模型,在临界运行点推导了输电能力对支路电抗灵敏度的数学表达式,提出根据此灵敏度排序结果确定可控串联补偿器(thyristor controlled series cap...支路传输功率、节点电压等的越限是制约系统输电能力提高的重要因素,为此文章采用连续潮流模型,在临界运行点推导了输电能力对支路电抗灵敏度的数学表达式,提出根据此灵敏度排序结果确定可控串联补偿器(thyristor controlled series capacitor,TCSC)安装地点的新方法。该方法中,TCSC安装位置确定以后,将安装TCSC之前发生越界的不等式约束在其边界值处用等式形式表示出来,并设定为已知条件,将TCSC对其所要安装支路的补偿度设定为一个新的未知量,扩展常规潮流方程,以求取扩展潮流不匹配函数的最小值为目标,计算支路的最优补偿度。对IEEE30节点和IEEE118节点系统的仿真计算结果表明该文所提出的选址和定容方法是有效的。展开更多
An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasit...An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.展开更多
基金Supported by the Doctoral Program Foundation of Institutions of Higher Education of China (No.20120111120008)State Key Lab of ASIC & System(Fudan University) (No. 11KF001)Special Fund for Doctoral Program (Hefei University of Technology) (No.2011HGBZ0953)
文摘A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.
基金The National Science Fund for Creative Re-search Groups( Grant No 60521002 )Shanghai Natural Science Foundation (GrantNo 037062022)
文摘A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.
基金supported by the National Natural Science Foundation of China(Nos.61036004,61076024)
文摘A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed.This structure is based on associating two sets of two capacitors in cross series during the amplification phase.This circuit permits the common-mode voltage of the sample signal to reach full swing.Using the charge-complement technique,the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively.Simulation results show that as sample signal common-mode voltage changes,the difference between the minimum and maximum gain error is less than 0.03%.When the capacitor mismatch is increased from 0 to 0.2%,the gain error is deteriorated by 0.00015%）.In all simulations,the gain of amplifier is 69 dB.
文摘A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.
文摘支路传输功率、节点电压等的越限是制约系统输电能力提高的重要因素,为此文章采用连续潮流模型,在临界运行点推导了输电能力对支路电抗灵敏度的数学表达式,提出根据此灵敏度排序结果确定可控串联补偿器(thyristor controlled series capacitor,TCSC)安装地点的新方法。该方法中,TCSC安装位置确定以后,将安装TCSC之前发生越界的不等式约束在其边界值处用等式形式表示出来,并设定为已知条件,将TCSC对其所要安装支路的补偿度设定为一个新的未知量,扩展常规潮流方程,以求取扩展潮流不匹配函数的最小值为目标,计算支路的最优补偿度。对IEEE30节点和IEEE118节点系统的仿真计算结果表明该文所提出的选址和定容方法是有效的。
基金Supported by National Science and Technology Major Project of China(No.2012ZX03004008)
文摘An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.
