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一种嵌入式微控制器的指令Cache设计方案
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作者 王睿 张艳花 《电子制作》 2025年第4期22-25,共4页
在传统的指令Cache设计方案中,VTag存储器大小取决于处理器的总线宽度以及指令Cache的Cache行数和Cache行大小。本文提出了一种优化指令Cache的电路设计,通过减小指令Cache覆盖的取指空间,在不影响指令Cache对外接口的总线宽度以及Cach... 在传统的指令Cache设计方案中,VTag存储器大小取决于处理器的总线宽度以及指令Cache的Cache行数和Cache行大小。本文提出了一种优化指令Cache的电路设计,通过减小指令Cache覆盖的取指空间,在不影响指令Cache对外接口的总线宽度以及Cache行数和Cache大小的情况下,进一步减小了VTag存储器的大小。本文用DC(Design Compiler)对指令Cache进行综合,结果表明,本文设计实现的指令Cache较传统方案在减少芯片面积的同时,显著提升了电路频率,对嵌入式微控制器的指令Cache设计具有重要的实用价值。 展开更多
关键词 嵌入式 微控制器 处理器 指令cache
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Rubyphi:面向gem5的Cache一致性协议自动化模型检验
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作者 徐学政 方健 +4 位作者 梁少杰 王璐 黄安文 隋京高 李琼 《计算机工程与科学》 北大核心 2025年第7期1141-1151,共11页
Cache一致性协议是多核系统数据一致性的保障,也直接影响内存子系统的性能,一直是微处理器设计和验证的重点。Cache一致性协议的设计和优化通常需借助gem5等软件模拟器快速实现。同时,由于协议设计中存在的错误在仿真测试中具有难触发... Cache一致性协议是多核系统数据一致性的保障,也直接影响内存子系统的性能,一直是微处理器设计和验证的重点。Cache一致性协议的设计和优化通常需借助gem5等软件模拟器快速实现。同时,由于协议设计中存在的错误在仿真测试中具有难触发、难定位和难修复的特点,需借助Murphi等模型检验工具进行形式化验证。然而,基于模拟器的协议设计优化和基于模型检验的协议验证在编程语言和抽象层次上存在巨大差异,设计者需要分别进行模拟器实现和模型检验建模,这不仅增加了时间成本,也为二者的等价性带来了隐患。设计并实现了面向gem5模拟器的Cache一致性协议自动化模型检验方法Rubyphi,通过提取gem5中实现的协议,自动完成基于Murphi的模型检验建模,进而对协议进行形式化验证。实验表明,Rubyphi能够有效地完成gem5中一致性协议的建模和验证,并成功发现了2个gem5现有协议中存在的错误,相关问题和解决方案已得到社区确认。 展开更多
关键词 cache一致性协议 多核处理器 模型检验 形式化验证
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FlyCache:Recommendation-driven edge caching architecture for full life cycle of video streaming
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作者 Shaohua Cao Quancheng Zheng +4 位作者 Zijun Zhan Yansheng Yang Huaqi Lv Danyang Zheng Weishan Zhang 《Digital Communications and Networks》 2025年第4期961-973,共13页
With the rapid development of 5G technology,the proportion of video traffic on the Internet is increasing,bringing pressure on the network infrastructure.Edge computing technology provides a feasible solution for opti... With the rapid development of 5G technology,the proportion of video traffic on the Internet is increasing,bringing pressure on the network infrastructure.Edge computing technology provides a feasible solution for optimizing video content distribution.However,the limited edge node cache capacity and dynamic user requests make edge caching more complex.Therefore,we propose a recommendation-driven edge Caching network architecture for the Full life cycle of video streaming(FlyCache)designed to improve users’Quality of Experience(QoE)and reduce backhaul traffic consumption.FlyCache implements intelligent caching management across three key stages:before-playback,during-playback,and after-playback.Specifically,we introduce a cache placement policy for the before-playback stage,a dynamic prefetching and cache admission policy for the during-playback stage,and a progressive cache eviction policy for the after-playback stage.To validate the effectiveness of FlyCache,we developed a user behavior-driven edge caching simulation framework incorporating recommendation mechanisms.Experiments conducted on the MovieLens and synthetic datasets demonstrate that FlyCache outperforms other caching strategies in terms of byte hit rate,backhaul traffic,and delayed startup rate. 展开更多
关键词 Edge caching cache architecture cache placement cache admission Caching eviction
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An Efficient Content Caching Strategy for Fog-Enabled Road Side Units in Vehicular Networks
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作者 Faareh Ahmed Babar Mansoor +1 位作者 Muhammad Awais Javed Abdul Khader Jilani Saudagar 《Computer Modeling in Engineering & Sciences》 2025年第9期3783-3804,共22页
Vehicular networks enable seamless connectivity for exchanging emergency and infotainment content.However,retrieving infotainment data from remote servers often introduces high delays,degrading the Quality of Service(... Vehicular networks enable seamless connectivity for exchanging emergency and infotainment content.However,retrieving infotainment data from remote servers often introduces high delays,degrading the Quality of Service(QoS).To overcome this,caching frequently requested content at fog-enabled Road Side Units(RSUs)reduces communication latency.Yet,the limited caching capacity of RSUs makes it impractical to store all contents with varying sizes and popularity.This research proposes an efficient content caching algorithm that adapts to dynamic vehicular demands on highways to maximize request satisfaction.The scheme is evaluated against Intelligent Content Caching(ICC)and Random Caching(RC).The obtained results show that our proposed scheme entertains more contentrequesting vehicles as compared to ICC and RC,with 33%and 41%more downloaded data in 28%and 35%less amount of time from ICC and RC schemes,respectively. 展开更多
关键词 Vehicular networks fog computing content caching infotainment services
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Age-Optimal Cached Distribution in the Satellite-Integrated Internet of Things via Cross-Slot Directed Graph
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作者 Hu Zhouyong Li Yue +1 位作者 Zhang Hanxu Yang Zhihua 《China Communications》 2025年第6期300-318,共19页
In the Satellite-integrated Internet of Things(S-IoT),data freshness in the time-sensitive scenarios could not be guaranteed over the timevarying topology with current distribution strategies aiming to reduce the tran... In the Satellite-integrated Internet of Things(S-IoT),data freshness in the time-sensitive scenarios could not be guaranteed over the timevarying topology with current distribution strategies aiming to reduce the transmission delay.To address this problem,in this paper,we propose an age-optimal caching distribution mechanism for the high-timeliness data collection in S-IoT by adopting a freshness metric,as called age of information(AoI)through the caching-based single-source multidestinations(SSMDs)transmission,namely Multi-AoI,with a well-designed cross-slot directed graph(CSG).With the proposed CSG,we make optimizations on the locations of cache nodes by solving a nonlinear integer programming problem on minimizing Multi-AoI.In particular,we put up forward three specific algorithms respectively for improving the Multi-AoI,i.e.,the minimum queuing delay algorithm(MQDA)based on node deviation from average level,the minimum propagation delay algorithm(MPDA)based on the node propagation delay reduction,and a delay balanced algorithm(DBA)based on node deviation from average level and propagation delay reduction.The simulation results show that the proposed mechanism can effectively improve the freshness of information compared with the random selection algorithm. 展开更多
关键词 age of information cached distribution satellite-integrated internet of things time-varying graph
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Adaptive multilevel fuzzy-based authentication framework to mitigate Cache side channel attack in cloud computing
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作者 Bharati Ainapure Deven Shah A.Ananda Rao 《International Journal of Modeling, Simulation, and Scientific Computing》 EI 2018年第5期174-194,共21页
Cloud computing supports multitenancy to satisfy the users’demands for accessing resources and simultaneously it increases revenue for cloud providers.Cloud providers adapt multitenancy by virtualizing the resources,... Cloud computing supports multitenancy to satisfy the users’demands for accessing resources and simultaneously it increases revenue for cloud providers.Cloud providers adapt multitenancy by virtualizing the resources,like CPU,network interfaces,peripherals,hard drives and memory using hypervisor to fulfill the demand.In a virtualized environment,many virtual machines(VMs)can run on the same core with the help of the hypervisor by sharing the resources.The VMs running on the same core are the target for the malicious or abnormal attacks like side channel attacks.Among various side channel attacks in cloud computing,cache-based side channel attack is one that leaks private information of the users based on the shared resources.Here,as the shared resource is the cache,a process can utilize the cache usage of another by cache contention.Cache sharing provides a way for the attackers to gain considerable information so that the key used for encryption can be inferred.Discovering this side channel attack is a challenging task.This requires identification of a feature that influences the attack.Even though there are various techniques available in the literature to mitigate such attacks,an effective solution to reduce the cache-based side channel attack is still an issue.Therefore,a novel fuzzy rule-based mechanism is integrated to detect the cache side channel attackers by monitoring the cache data access(CDA).The factor that determines the attack is CDA in a log file created by the framework during authorization.The proposed framework also utilizes certain security properties including ECC and hashing for the privacy preservation and the decision is made with the aid of a fuzzy logic system. 展开更多
关键词 cache side channel attack shared resources fuzzy ECC HASHING registration authorization.
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多核处理器共享Cache的划分算法 被引量:1
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作者 吕海玉 罗广 +1 位作者 朱嘉炜 张凤登 《电子科技》 2024年第9期27-33,共7页
针对多核处理器性能优化问题,文中深入研究多核处理器上共享Cache的管理策略,提出了基于缓存时间公平性与吞吐率的共享Cache划分算法MT-FTP(Memory Time based Fair and Throughput Partitioning)。以公平性和吞吐率两个评价性指标建立... 针对多核处理器性能优化问题,文中深入研究多核处理器上共享Cache的管理策略,提出了基于缓存时间公平性与吞吐率的共享Cache划分算法MT-FTP(Memory Time based Fair and Throughput Partitioning)。以公平性和吞吐率两个评价性指标建立数学模型,并分析了算法的划分流程。仿真实验结果表明,MT-FTP算法在系统吞吐率方面表现较好,其平均IPC(Instructions Per Cycles)值比UCP(Use Case Point)算法高1.3%,比LRU(Least Recently Used)算法高11.6%。MT-FTP算法对应的系统平均公平性比LRU算法的系统平均公平性高17%,比UCP算法的平均公平性高16.5%。该算法实现了共享Cache划分公平性并兼顾了系统的吞吐率。 展开更多
关键词 片上多核处理器 内存墙 划分 公平性 吞吐率 共享cache 缓存时间 集成计算机
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GFCache: A Greedy Failure Cache Considering Failure Recency and Failure Frequency for an Erasure-Coded Storage System
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作者 Mingzhu Deng Fang Liu +2 位作者 Ming Zhao Zhiguang Chen Nong Xiao 《Computers, Materials & Continua》 SCIE EI 2019年第1期153-167,共15页
In the big data era,data unavailability,either temporary or permanent,becomes a normal occurrence on a daily basis.Unlike the permanent data failure,which is fixed through a background job,temporarily unavailable data... In the big data era,data unavailability,either temporary or permanent,becomes a normal occurrence on a daily basis.Unlike the permanent data failure,which is fixed through a background job,temporarily unavailable data is recovered on-the-fly to serve the ongoing read request.However,those newly revived data is discarded after serving the request,due to the assumption that data experiencing temporary failures could come back alive later.Such disposal of failure data prevents the sharing of failure information among clients,and leads to many unnecessary data recovery processes,(e.g.caused by either recurring unavailability of a data or multiple data failures in one stripe),thereby straining system performance.To this end,this paper proposes GFCache to cache corrupted data for the dual purposes of failure information sharing and eliminating unnecessary data recovery processes.GFCache employs a greedy caching approach of opportunism to promote not only the failed data,but also sequential failure-likely data in the same stripe.Additionally,GFCache includes a FARC(Failure ARC)catch replacement algorithm,which features a balanced consideration of failure recency,frequency to accommodate data corruption with good hit ratio.The stored data in GFCache is able to support fast read of the normal data access.Furthermore,since GFCache is a generic failure cache,it can be used anywhere erasure coding is deployed with any specific coding schemes and parameters.Evaluations show that GFCache achieves good hit ratio with our sophisticated caching algorithm and manages to significantly boost system performance by reducing unnecessary data recoveries with vulnerable data in the cache. 展开更多
关键词 FAILURE cache GREEDY recovery ERASURE coding FAILURE RECENCY FAILURE frequency
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A Cache Considering Role-Based Access Control and Trust in Privilege Management Infrastructure
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作者 ZHANG Shaomin WANG Baoyi ZHOU Lihua 《Wuhan University Journal of Natural Sciences》 CAS 2006年第6期1827-1830,共4页
PMI (privilege management infrastructure) is used to perform access control to resource in an E-commerce or E-government system. With the ever-increasing need for secure transaction, the need for systems that offer ... PMI (privilege management infrastructure) is used to perform access control to resource in an E-commerce or E-government system. With the ever-increasing need for secure transaction, the need for systems that offer a wide variety of QoS (quality-of-service) features is also growing. In order to improve the QoS of PMI system, a cache based on RBAC (Role-based Access control) and trust is proposed. Our system is realized based on Web service. How to design the cache based on RBAC and trust in the access control model is deseribed in detail. The algorithm to query role permission in cache and to add records in cache is dealt with. The policy to update cache is introduced also. 展开更多
关键词 access control RBAC(role-based access controd TRUST cache PMI (privilege management infrastructure)
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基于Cache优化的服务调用方法
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作者 杨国胜 杨毅 +1 位作者 王海 段锴 《数字技术与应用》 2024年第4期60-63,共4页
集中式服务网关通常使用共享内存进行服务实例与治理参数的本地化生产与消费,实现业务处理与服务发现逻辑的解耦,增强系统的稳定性,但频繁的共享内存操作往往带来系统资源利用率和请求处理耗时上的低效。通过引入缓存机制,在服务网关的... 集中式服务网关通常使用共享内存进行服务实例与治理参数的本地化生产与消费,实现业务处理与服务发现逻辑的解耦,增强系统的稳定性,但频繁的共享内存操作往往带来系统资源利用率和请求处理耗时上的低效。通过引入缓存机制,在服务网关的路由组件内部实现并利用针对服务调用优化的Cache,热点数据请求直接从Cache中读取结构化信息,避免了共享内存操作与存储块的编解码,有效地利用缓存空间,提高了数据访问速度,同时减少了共享内存操作中的资源竞争,提高了系统并发。 展开更多
关键词 共享内存 服务网关 缓存机制 服务实例 cache 结构化信息 热点数据 缓存空间
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R-DSP中二级Cache控制器的优化设计
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作者 谭露露 谭勋琼 白创 《电子与封装》 2024年第7期63-68,共6页
针对二级Cache控制器(L2)对于提升R数字信号处理器(R-DSP)访存效率和整体性能的重要作用,结合L2中涉及的内存安全维护和多请求访存仲裁问题,在现有R-DSP中L2基础上实现优化。首先,采用多重分块的存储组织结构,提高访存效率;其次,并行处... 针对二级Cache控制器(L2)对于提升R数字信号处理器(R-DSP)访存效率和整体性能的重要作用,结合L2中涉及的内存安全维护和多请求访存仲裁问题,在现有R-DSP中L2基础上实现优化。首先,采用多重分块的存储组织结构,提高访存效率;其次,并行处理一级Cache控制器请求与外存请求,减小请求处理周期;最后,增加带宽管理与存储保护功能,合理仲裁访存请求并维护存储安全。实验结果表明,相较于传统设计,新设计在保护二级存储安全的同时实现带宽管理式访存仲裁。与现有R-DSP中的L2相比,新设计的存储体单拍最大可响应访存请求数量提升了1倍,一级请求和外存请求的平均处理时钟周期数分别降低了25%和19.6%。 展开更多
关键词 DSP 二级cache 存储结构 并行处理 存储保护 带宽管理
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Efficient cache replacement framework based on access hotness for spacecraft processors
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作者 GAO Xin NIAN Jiawei +1 位作者 LIU Hongjin YANG Mengfei 《中国空间科学技术(中英文)》 CSCD 北大核心 2024年第2期74-88,共15页
A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity... A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity of contemporary high-performance spacecraft processors.To harness these non-uniform access behaviors,an efficient cache replacement framework featuring an auxiliary cache specifically designed to retain evicted hot data was proposed.This framework reconstructs the cache replacement policy,facilitating data migration between the main cache and the auxiliary cache.Unlike traditional cacheline-granularity policies,the approach excels at identifying and evicting infrequently used data,thereby optimizing cache utilization.The evaluation shows impressive performance improvement,especially on workloads with irregular access patterns.Benefiting from fine granularity,the proposal achieves superior storage efficiency compared with commonly used cache management schemes,providing a potential optimization opportunity for modern resource-constrained processors,such as spacecraft processors.Furthermore,the framework complements existing modern cache replacement policies and can be seamlessly integrated with minimal modifications,enhancing their overall efficacy. 展开更多
关键词 spacecraft processors cache management replacement policy storage efficiency memory hierarchy MICROARCHITECTURE
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EBCache:A Novel Cache-Based Mechanism for Mitigating the Spectre Attacks for RISC-V Processor
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作者 Wu Dehua Xiao Wan’ang Gao Wanlin 《China Communications》 SCIE CSCD 2024年第12期166-185,共20页
The cache-based covert channel is one of the common vulnerabilities exploited in the Spectre attacks.Current mitigation strategies focus on blocking the eviction-based channel by using a random/encrypted mapping funct... The cache-based covert channel is one of the common vulnerabilities exploited in the Spectre attacks.Current mitigation strategies focus on blocking the eviction-based channel by using a random/encrypted mapping function to translate memory address to the cache address,while the updated-based channel is still vulnerable.In addition,some mitigation strategies are also costly as it needs software and hardware modifications.In this paper,our objective is to devise low-cost,comprehensive-protection techniques for mitigating the Spectre attacks.We proposed a novel cache structure,named EBCache,which focuses on the RISC-V processor and applies the address encryption and blacklist to resist the Spectre attacks.The addresses encryption mechanism increases the difficulty of pruning a minimal eviction set.The blacklist mechanism makes the updated cache lines loaded by the malicious updates invisible.Our experiments demonstrated that the EBCache can prevent malicious modifications.The EBCache,however,reduces the processor’s performance by about 23%but involves only a low-cost modification in the hardware. 展开更多
关键词 cache structure out-of-order execution side-channel attacks the Spectre attacks
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Cache侧信道攻击防御量化研究
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作者 王占鹏 朱子元 王立敏 《信息安全学报》 CSCD 2024年第4期107-124,共18页
芯片安全防护技术关系到国家、企业和个人的信息安全,相关的研究一直是计算机安全领域的热点。片上高速缓存对芯片性能起着重要作用,可以有效提升芯片内核访问效率。传统的缓存设计并没有充分考虑安全性,侧信道攻击会对Cache造成巨大威... 芯片安全防护技术关系到国家、企业和个人的信息安全,相关的研究一直是计算机安全领域的热点。片上高速缓存对芯片性能起着重要作用,可以有效提升芯片内核访问效率。传统的缓存设计并没有充分考虑安全性,侧信道攻击会对Cache造成巨大威胁,可以窃取加密密钥等内存存储敏感信息。攻击者利用侧信道的技术窃取用户的隐私数据或加密算法密钥时不会改变片上系统芯片的运行状态,从而使计算机系统很难检测是否受到了攻击。与基于电磁信号和基于能量检测的侧信道攻击相比,基于存储共享的侧信道攻击只需要利用软件测量就可以实现,对芯片安全的威胁更大。目前存在多种侧信道攻击和防御手段,但缺乏一套完善的关于系统架构的安全度量方法,对Cache的安全性进行有效评估。本文对Cache侧信道攻击和防御手段进行模型化分析,提出一套Cache安全性量化研究方法。首先,我们采用CVSS漏洞评分模型对Cache侧信道攻击进行量化评分。然后,利用贝叶斯公式,构建侧信道攻击和防御的关系模型。最后,通过图模型对Cache侧信道攻击机理进行建模,计算在防御架构基础上不同威胁的攻击成功率,并结合CVSS防御得分求得不同防御方法的得分。本文针对Cache侧信道攻击进行机理建模,对攻击和防御进行评估和探索,为硬件安全人员提供理论支持。 展开更多
关键词 cache侧信道 CVSS 贝叶斯模型 安全量化 安全架构
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一种带Cache加速的HyperRAM控制器设计与验证
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作者 邹敏 鲁澳宇 +1 位作者 邹望辉 喻华 《现代电子技术》 北大核心 2024年第6期91-96,共6页
针对目前可穿戴设备上对存储设备性能要求高、体积小、功耗低等问题,在FPGA上实现了一款可拓展的高性能HyperRAM控制器,并引入Cache缓存加速设计,以提高对频繁访问数据的命中率和优化存储器访问模式,实现更高速的数据传输和优化的系统... 针对目前可穿戴设备上对存储设备性能要求高、体积小、功耗低等问题,在FPGA上实现了一款可拓展的高性能HyperRAM控制器,并引入Cache缓存加速设计,以提高对频繁访问数据的命中率和优化存储器访问模式,实现更高速的数据传输和优化的系统性能。运用UVM验证方法学和FPGA进行验证,结果表明,带有Cache缓存的HyperRAM控制器相较于普通HyperRAM,在读写连续地址时性能提高61%,并具有较好的可靠性与有效性,可为嵌入式系统提供高效、灵活的存储器解决方案。 展开更多
关键词 HyperRAM控制器 cache缓存 可穿戴设备 存储器 UVM验证方法学 FPGA
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Intelligent cache and buffer optimization for mobile VR adaptive transmission in 5G edge computing networks
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作者 Junchao Yang Ali Kashif Bashir +2 位作者 Zhiwei Guo Keping Yu Mohsen Guizani 《Digital Communications and Networks》 CSCD 2024年第5期1234-1244,共11页
Virtual Reality(VR)is a key industry for the development of the digital economy in the future.Mobile VR has advantages in terms of mobility,lightweight and cost-effectiveness,which has gradually become the mainstream ... Virtual Reality(VR)is a key industry for the development of the digital economy in the future.Mobile VR has advantages in terms of mobility,lightweight and cost-effectiveness,which has gradually become the mainstream implementation of VR.In this paper,a mobile VR video adaptive transmission mechanism based on intelligent caching and hierarchical buffering strategy in Mobile Edge Computing(MEC)-equipped 5G networks is proposed,aiming at the low latency requirements of mobile VR services and flexible buffer management for VR video adaptive transmission.To support VR content proactive caching and intelligent buffer management,users’behavioral similarity and head movement trajectory are jointly used for viewpoint prediction.The tile-based content is proactively cached in the MEC nodes based on the popularity of the VR content.Second,a hierarchical buffer-based adaptive update algorithm is presented,which jointly considers bandwidth,buffer,and predicted viewpoint status to update the tile chunk in client buffer.Then,according to the decomposition of the problem,the buffer update problem is modeled as an optimization problem,and the corresponding solution algorithms are presented.Finally,the simulation results show that the adaptive caching algorithm based on 5G intelligent edge and hierarchical buffer strategy can improve the user experience in the case of bandwidth fluctuations,and the proposed viewpoint prediction method can significantly improve the accuracy of viewpoint prediction by 15%. 展开更多
关键词 Virtual reality Adaptive transmission Edge cache Buffer management 5G Mobile edge computing
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Analytical modeling of cache-enabled heterogeneous networks using Poisson cluster processes
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作者 Junhui Zhao Lihua Yang +1 位作者 Xiaoting Ma Ziyang Zhang 《Digital Communications and Networks》 CSCD 2024年第5期1439-1447,共9页
The dual frequency Heterogeneous Network(HetNet),including sub-6 GHz networks together with Millimeter Wave(mmWave),achieves the high data rates of user in the networks with hotspots.The cache-enabled HetNets with hot... The dual frequency Heterogeneous Network(HetNet),including sub-6 GHz networks together with Millimeter Wave(mmWave),achieves the high data rates of user in the networks with hotspots.The cache-enabled HetNets with hotspots are investigated using an analytical framework in which Macro Base Stations(MBSs)and hotspot centers are treated as two independent homogeneous Poisson Point Processes(PPPs),and locations of Small Base Stations(SBSs)and users are modeled as two Poisson Cluster Processes(PCPs).Under the PCP-based modeling method and the Most Popular Caching(MPC)scheme,we propose a cache-enabled association strategy for HetNets with limited storage capacity.The performance of association probability and coverage probability is explicitly derived,and Monte Carlo simulation is utilized to verify that the results are correct.The outcomes of the simulation present the influence of antenna configuration and cache capacities of MBSs and SBSs on network performance.Numerical optimization of the standard deviation ratio of SBSs and users of association probability is enabled by our analysis. 展开更多
关键词 Heterogeneous networks Millimeter wave Poisson cluster processes CACHING Stochastic geometry
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符合粒子输运模拟的专用加速器体系结构
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作者 张建民 刘津津 +1 位作者 许炜康 黎铁军 《国防科技大学学报》 北大核心 2025年第2期155-164,共10页
粒子输运模拟是高性能计算机的主要应用,对于其日益增长的计算规模需求,通用微处理器由于其单核结构复杂,无法适应程序特征,难以获得较高的性能功耗比。因此,对求解粒子输运非确定性数值模拟的程序特征进行提取与分析;基于算法特征,对... 粒子输运模拟是高性能计算机的主要应用,对于其日益增长的计算规模需求,通用微处理器由于其单核结构复杂,无法适应程序特征,难以获得较高的性能功耗比。因此,对求解粒子输运非确定性数值模拟的程序特征进行提取与分析;基于算法特征,对开源微处理器内核架构进行定制设计,包括加速器流水线结构、分支预测部件、多级Cache层次与主存设计,构建一种符合粒子输运程序特征的专用加速器体系结构。在业界通用体系结构模拟器上运行粒子输运程序的模拟结果表明,与ARM Cortex-A15相比,所提出的专用加速器体系结构在同等功耗下可获得4.6倍的性能提升,在同等面积下可获得3.2倍的性能提升。 展开更多
关键词 粒子输运模拟 专用加速器 程序特征 分支预测 多级cache
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一种高性能PCIe接口设计与实现
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作者 张梅娟 辛昆鹏 周迁 《现代电子技术》 北大核心 2025年第8期70-74,共5页
多款处理器在PCIe 2.0×4下传输速率不足理论带宽的20%,最高仅有380 MB/s,不能满足实际应用需求。为解决嵌入式处理器PCIe接口传输速率过低的问题,设计一款高性能PCIe接口,有效提高了接口数据传输速率。经性能瓶颈系统分析,增加设计... 多款处理器在PCIe 2.0×4下传输速率不足理论带宽的20%,最高仅有380 MB/s,不能满足实际应用需求。为解决嵌入式处理器PCIe接口传输速率过低的问题,设计一款高性能PCIe接口,有效提高了接口数据传输速率。经性能瓶颈系统分析,增加设计PCIe DMA与处理器Cache一致性功能,能解决DMA传输完成后软件Cache同步耗时严重的问题,使速率提升3.8倍,达到1 450 MB/s。在硬件设计上DMA支持链表模式,通过描述符链表将分散的内存集聚起来,一次DMA启动可完成多个非连续地址内存的数据传输,并优化与改进软件驱动中分散集聚DMA实现方式,充分利用硬件Cache一致性功能,进一步提升10%的传输速率,最终达到PCIe 2.0×4理论带宽的80%。此外,该PCIe接口采用多通道DMA的设计,最大支持8路独立DMA读写通道,可应用于多核多任务并行传输数据的应用场景,更进一步提升整体数据传输带宽。经验证,该PCIe接口具有良好的稳定性和高效性,最大可支持8通道数据并行传输,且单通道传输速率可达到理论速率的80%。 展开更多
关键词 PCIe接口 DMA控制器 高速数据传输 cache一致性 多通道设计 分散集聚 链表模式
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面向高性能DSP的一级可配置指令缓存设计与验证
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作者 唐俊龙 高睿禧 《集成电路与嵌入式系统》 2025年第5期24-34,共11页
针对程序运行中Cache无法有效预测非局部访问的问题,提出了一种基于二级存储结构的高安全性一级可配置指令缓存设计方案。该方案通过页与Cache行的两种粒度存储保护机制,确保不同级别用户的数据安全;实现了内部控制寄存器和灵活可配置的... 针对程序运行中Cache无法有效预测非局部访问的问题,提出了一种基于二级存储结构的高安全性一级可配置指令缓存设计方案。该方案通过页与Cache行的两种粒度存储保护机制,确保不同级别用户的数据安全;实现了内部控制寄存器和灵活可配置的Cache/SRAM结构,支持快速配置和扩展;利用直接存储访问模块实现了与外部存储的高效交互。通过UVM平台进行模块级验证,并对比不同L1P大小配置下的命中率,调用40 nm低阈值库验证了系统的时延和功耗性能。实验结果表明,所设计的缓存方案能在32 KB至0 KB五种L1P配置间快速切换,满足600 MHz高性能DSP的需求,最大路径延时为1.47 ns,总功耗为309.577 mW。 展开更多
关键词 一级指令缓存 UVM验证学 存储保护 DSP cache
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