FinFET technologies are becoming the mainstream process as technology scales down. Based on a 28-nm bulk p- FinFET device, we have investigated the fin width and height dependence of bipolar amplification for heavy-io...FinFET technologies are becoming the mainstream process as technology scales down. Based on a 28-nm bulk p- FinFET device, we have investigated the fin width and height dependence of bipolar amplification for heavy-ion-irradiated FinFETs by 3D TCAD numerical simulation. Simulation results show that due to a well bipolar conduction mechanism rather than a channel （fin） conduction path, the transistors with narrower fins exhibit a diminished bipolar amplification effect, while the fin height presents a trivial effect on the bipolar amplification and charge collection. The results also indicate that the single event transient （SET） pulse width can be mitigated about 35% at least by optimizing the ratio of fin width and height, which can provide guidance for radiation-hardened applications in bulk FinFET technology.展开更多
Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin F...Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer （PTSL） and source drain extension （SDE） doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function （EWF） MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device＇s scaling.展开更多
We investigate the influence of gate-source/drain （G-S/D） misalignment on the performance of bulk fin field effect transistors （FinFETs） through the three-dimensional （3D） full band Monte Carlo simulator. Severa...We investigate the influence of gate-source/drain （G-S/D） misalignment on the performance of bulk fin field effect transistors （FinFETs） through the three-dimensional （3D） full band Monte Carlo simulator. Several scat- tering mechanisms, such as acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are considered in our simulator. The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work. Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length. The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.展开更多
Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor （FinFET） technology. However, the studies of charge sharing induced single-event transient （SET） pulse q...Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor （FinFET） technology. However, the studies of charge sharing induced single-event transient （SET） pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design （3DTCAD） mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing （RBB）, the circuit with forward body-biasing （FBB） is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications.展开更多
In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanis...In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.展开更多
This paper reports the physical realization of the Bipolar Field-Effect Transistor （BiFET） and its onetransistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pur...This paper reports the physical realization of the Bipolar Field-Effect Transistor （BiFET） and its onetransistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor （the bulk transistor） and the impurethin-base Silicon-on-Insulator （SOI） transistor and the two-MOS-gates on thin base transistors （the FinFET and the Thin Film Transistor TFF）. Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.展开更多
基金supported by the National Natural Science of China(Grant No.61376109)
文摘FinFET technologies are becoming the mainstream process as technology scales down. Based on a 28-nm bulk p- FinFET device, we have investigated the fin width and height dependence of bipolar amplification for heavy-ion-irradiated FinFETs by 3D TCAD numerical simulation. Simulation results show that due to a well bipolar conduction mechanism rather than a channel （fin） conduction path, the transistors with narrower fins exhibit a diminished bipolar amplification effect, while the fin height presents a trivial effect on the bipolar amplification and charge collection. The results also indicate that the single event transient （SET） pulse width can be mitigated about 35% at least by optimizing the ratio of fin width and height, which can provide guidance for radiation-hardened applications in bulk FinFET technology.
基金supported by the National 02 IC Projectsthe Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences
文摘Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer （PTSL） and source drain extension （SDE） doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function （EWF） MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device＇s scaling.
基金Project supported by the National Fundamental Basic Research Program of China(No.2011CBA00604)
文摘We investigate the influence of gate-source/drain （G-S/D） misalignment on the performance of bulk fin field effect transistors （FinFETs） through the three-dimensional （3D） full band Monte Carlo simulator. Several scat- tering mechanisms, such as acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are considered in our simulator. The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work. Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length. The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.
基金supported by the National Natural Science Foundation of China(Grant Nos.61376109,61434007,and 61176030)
文摘Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor （FinFET） technology. However, the studies of charge sharing induced single-event transient （SET） pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design （3DTCAD） mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing （RBB）, the circuit with forward body-biasing （FBB） is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications.
基金Project supported by the National Basic Research Program of China (Grant No. 2011CBA00604)
文摘In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.
基金This investigation and Jie Binbin have been supported by the CTSAH Associates (CTSA)founded by the late Linda Su-Nan Chang Sah,in memory of her 70th year.
文摘This paper reports the physical realization of the Bipolar Field-Effect Transistor （BiFET） and its onetransistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor （the bulk transistor） and the impurethin-base Silicon-on-Insulator （SOI） transistor and the two-MOS-gates on thin base transistors （the FinFET and the Thin Film Transistor TFF）. Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.
