To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（Σ...To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.展开更多
To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural networks （ANN） hardware implementation methods, a bit-stream ANN construction method based on direct sigma-delta （Z-A...To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural networks （ANN） hardware implementation methods, a bit-stream ANN construction method based on direct sigma-delta （Z-A） signal processing is presented. The bit-stream adder, multiplier and fully digital X-A modulator used in the bit-stream linear ANN are implemented in a field programmable gate array （FPGA）. A bit-stream linear ANN based on these bit-stream modules is presented and implemented. To verify the function and performance of the bit-stream linear ANN, the bit-stream adaptive predictor and the bit-stream adaptive noise cancellation system are presented. The predicted result of the bit-stream adaptive predictor is very close to the desired signal. Also, the bit-stream adaptive noise cancellation system removes the electric power noise effectively.展开更多
In the process of protected protocol recognition,an improved AGglomerative NESting algorithm( IAGNES) with high adaptability is proposed,which is based on the AGglomerative NESting algorithm( AGNES),for the challengin...In the process of protected protocol recognition,an improved AGglomerative NESting algorithm( IAGNES) with high adaptability is proposed,which is based on the AGglomerative NESting algorithm( AGNES),for the challenging issue of how to obtain single protocol data frames from multiprotocol data frames. It can improve accuracy and efficiency by similarity between bit-stream data frames and clusters,extract clusters in the process of clustering. Every cluster obtained contains similarity evaluation index which is helpful to evaluation. More importantly,IAGNES algorithm can automatically recognize the number of cluster. Experiments on the data set published by Lincoln Laboratory shows that the algorithm can cluster the protocol data frames with high accuracy.展开更多
The evolution of 5G and beyond wireless networks has intensified the demand for millimeterwave technology to support high-throughput applications.This paper introduces a novel energy-efficient digital beamforming rece...The evolution of 5G and beyond wireless networks has intensified the demand for millimeterwave technology to support high-throughput applications.This paper introduces a novel energy-efficient digital beamforming receiver architecture that integrates multi-stage noise-shaping(MASH)delta-sigma modulators(DSMs)with bit-stream processing(BSP),effectively addressing the significant propagation losses and dynamic electromagnetic interference associated with millimeter-wave(mm-wave)systems.The novel architecture achieves enhanced dynamic range without increasing signal bit-width,thereby ensuring low power consumption and a compact design.Unlike traditional analog and hybrid beamforming methods,the proposed approach utilizes digital-domain processing for precise beamforming,simplified local oscillator networks,and improved integration.System-level simulations with a 9-antenna beamforming receiver array demonstrate the architecture’s capability for accurate beamforming across angles from 30°to 150°and effective dual-target detection.Furthermore,the P2S-BSP architecture reduces digital circuitry area by 50%compared to previous implementations while maintaining energy efficiency.These advancements highlight the proposed architecture as a scalable solution for future mm-wave applications,including intelligent transportation systems,radar,and high-density mobile networks.展开更多
Most of the industrial model-based predictive control algorithms are suffering from heavy computation burden when solving the QR optimizations and on-line matrixes multiplication within a limited sampling step.In orde...Most of the industrial model-based predictive control algorithms are suffering from heavy computation burden when solving the QR optimizations and on-line matrixes multiplication within a limited sampling step.In order to optimize this problem,a fast algorithm is proposed,which the real-time values are modulated into bit streams to simplify the multiplication as the bit based operation could extremely decrease the compute consumption.In addition,the control variables are deduced from the prediction horizon to the current control actuation approximately by a recursive relation instead of figuring all of the control actuations out strictly to reduce the matrix dimension.展开更多
The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-s...The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC＇s 0.18-μm CMOS process.The chip area is 475×570μm^2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.展开更多
An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its su...An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.展开更多
基金The National Natural Science Foundation of China (No.60576028)the Natural Science Foundation of Higher Education Institutions of Jiangsu Province(No.11KJB510004)
文摘To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.
基金Supported by the National Natural Science Foundation of China （No. 60576028） and the National High Technology Research and Development Program of China （No. 2007AA01Z2a5）
文摘To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural networks （ANN） hardware implementation methods, a bit-stream ANN construction method based on direct sigma-delta （Z-A） signal processing is presented. The bit-stream adder, multiplier and fully digital X-A modulator used in the bit-stream linear ANN are implemented in a field programmable gate array （FPGA）. A bit-stream linear ANN based on these bit-stream modules is presented and implemented. To verify the function and performance of the bit-stream linear ANN, the bit-stream adaptive predictor and the bit-stream adaptive noise cancellation system are presented. The predicted result of the bit-stream adaptive predictor is very close to the desired signal. Also, the bit-stream adaptive noise cancellation system removes the electric power noise effectively.
基金Supported by the National Natural Science Foundation of China(No.F020704)
文摘In the process of protected protocol recognition,an improved AGglomerative NESting algorithm( IAGNES) with high adaptability is proposed,which is based on the AGglomerative NESting algorithm( AGNES),for the challenging issue of how to obtain single protocol data frames from multiprotocol data frames. It can improve accuracy and efficiency by similarity between bit-stream data frames and clusters,extract clusters in the process of clustering. Every cluster obtained contains similarity evaluation index which is helpful to evaluation. More importantly,IAGNES algorithm can automatically recognize the number of cluster. Experiments on the data set published by Lincoln Laboratory shows that the algorithm can cluster the protocol data frames with high accuracy.
基金supported by the Chinese National Natural Science Foundation under Grant 62431016Grant 62122051.
文摘The evolution of 5G and beyond wireless networks has intensified the demand for millimeterwave technology to support high-throughput applications.This paper introduces a novel energy-efficient digital beamforming receiver architecture that integrates multi-stage noise-shaping(MASH)delta-sigma modulators(DSMs)with bit-stream processing(BSP),effectively addressing the significant propagation losses and dynamic electromagnetic interference associated with millimeter-wave(mm-wave)systems.The novel architecture achieves enhanced dynamic range without increasing signal bit-width,thereby ensuring low power consumption and a compact design.Unlike traditional analog and hybrid beamforming methods,the proposed approach utilizes digital-domain processing for precise beamforming,simplified local oscillator networks,and improved integration.System-level simulations with a 9-antenna beamforming receiver array demonstrate the architecture’s capability for accurate beamforming across angles from 30°to 150°and effective dual-target detection.Furthermore,the P2S-BSP architecture reduces digital circuitry area by 50%compared to previous implementations while maintaining energy efficiency.These advancements highlight the proposed architecture as a scalable solution for future mm-wave applications,including intelligent transportation systems,radar,and high-density mobile networks.
文摘Most of the industrial model-based predictive control algorithms are suffering from heavy computation burden when solving the QR optimizations and on-line matrixes multiplication within a limited sampling step.In order to optimize this problem,a fast algorithm is proposed,which the real-time values are modulated into bit streams to simplify the multiplication as the bit based operation could extremely decrease the compute consumption.In addition,the control variables are deduced from the prediction horizon to the current control actuation approximately by a recursive relation instead of figuring all of the control actuations out strictly to reduce the matrix dimension.
基金Project supported by the National Natural Science Foundation of China(No.60576028).
文摘The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC＇s 0.18-μm CMOS process.The chip area is 475×570μm^2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.
基金supported by the National Natural Science Foundation of China(No.60576028)
文摘An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.
