BACKGROUND Effective health management for high-risk stroke populations is essential.The hospital-community-home(HCH)collaborative health management(CHM)model leverages resources from hospitals,communities,and familie...BACKGROUND Effective health management for high-risk stroke populations is essential.The hospital-community-home(HCH)collaborative health management(CHM)model leverages resources from hospitals,communities,and families.By integrating patient information across these three domains,it facilitates the delivery of tailored guidance,health risk assessments,and three-in-one health education.AIM To explore the effects of the HCH-CHM model on stroke risk reduction in highrisk populations.METHODS In total,110 high-risk stroke patients screened in the community from January 2019 to January 2023 were enrolled,with 52 patients in the control group receiving routine health education and 58 in the observation group receiving HCH-CHM model interventions based on routine health education.Stroke awareness scores,health behavior levels,medication adherence,blood pressure,serum biochemical markers(systolic/diastolic blood pressure,total cholesterol,and triglyceride),and psychological measures(self-rating anxiety/depression scale)were evaluated and compared between groups.RESULTS The observation group showed statistically significant improvements in stroke awareness scores and health behavior levels compared to the control group(P<0.05),with notable enhancements in lifestyle and dietary habits(P<0.05)and reductions in postintervention systolic blood pressure,diastolic blood pressure,total cholesterol,triglyceride,self-rating anxiety scale,and self-rating depression scale scores(P<0.05).CONCLUSION The HCH-CHM model had a significant positive effect on high-risk stroke populations,effectively increasing disease awareness,improving health behavior and medication adherence,and appropriately ameliorating blood pressure,serum biochemical marker levels,and negative psychological symptoms.展开更多
Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behav...Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.展开更多
基金Supported by Guiding Project of Hebei Provincial Health Commission,No.20201190 and 20180220.
文摘BACKGROUND Effective health management for high-risk stroke populations is essential.The hospital-community-home(HCH)collaborative health management(CHM)model leverages resources from hospitals,communities,and families.By integrating patient information across these three domains,it facilitates the delivery of tailored guidance,health risk assessments,and three-in-one health education.AIM To explore the effects of the HCH-CHM model on stroke risk reduction in highrisk populations.METHODS In total,110 high-risk stroke patients screened in the community from January 2019 to January 2023 were enrolled,with 52 patients in the control group receiving routine health education and 58 in the observation group receiving HCH-CHM model interventions based on routine health education.Stroke awareness scores,health behavior levels,medication adherence,blood pressure,serum biochemical markers(systolic/diastolic blood pressure,total cholesterol,and triglyceride),and psychological measures(self-rating anxiety/depression scale)were evaluated and compared between groups.RESULTS The observation group showed statistically significant improvements in stroke awareness scores and health behavior levels compared to the control group(P<0.05),with notable enhancements in lifestyle and dietary habits(P<0.05)and reductions in postintervention systolic blood pressure,diastolic blood pressure,total cholesterol,triglyceride,self-rating anxiety scale,and self-rating depression scale scores(P<0.05).CONCLUSION The HCH-CHM model had a significant positive effect on high-risk stroke populations,effectively increasing disease awareness,improving health behavior and medication adherence,and appropriately ameliorating blood pressure,serum biochemical marker levels,and negative psychological symptoms.
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA010301)the Research Foundation of Zhongxing Telecom Equipment Corporation and the National Natural Science Foundation of China(No.60976029)
文摘Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.
