Properties of GaAs single crystals grown at low temperatures by molecular beam epitaxy (LTMBE GaAs) have been studied. The results show that excessive arsenic atoms of about 1020 cm?3 exist in LTMBE GaAs in the form o...Properties of GaAs single crystals grown at low temperatures by molecular beam epitaxy (LTMBE GaAs) have been studied. The results show that excessive arsenic atoms of about 1020 cm?3 exist in LTMBE GaAs in the form of arsenic interstitial couples, and cause the dilation in lattice parameter of LTMBE GaAs. The arsenic interstitial couples will be decomposed, and the excessive arsenic atoms will precipitate during the annealing above 300°C. Arsenic precipitates accumulate in the junctions of epilayers with the increase in the temperature of annealing. The depletion regions caused by arsenic precipitates overlap each other in LTMBE GaAs, taking on the character of high resistivity, and the effects of backgating or sidegating are effectively restrained.展开更多
We propose a novel backgate sandwich nanowire MOSFET （SNFET）, which offers the advantages of ETSOI （dynamic backgate voltage controllability） and nanowire FETs （good short channel effect）. A backgate is used for...We propose a novel backgate sandwich nanowire MOSFET （SNFET）, which offers the advantages of ETSOI （dynamic backgate voltage controllability） and nanowire FETs （good short channel effect）. A backgate is used for threshold voltage （Vt） control of the SNFET. Compared with a backgate FinFET with a punch-through stop layer （PTSL）, the SNFET possesses improved device performance. 3D device simulations indicate that the SNFET has a three times larger overdrive current, a -75% smaller off leakage current, and reduced subthreshold swing （SS） and DIBL than those of a backgate FinFET when the nanowire （NW） and the fin are of equal width. A new process flow to fabricate the backgate SNFET is also proposed in this work. Our analytical model suggests that Vt control by the backgate can be attributed to the capacitances formed by the frontgate, NW, and backgate. The SNFET devices are compatible with the latest state-of-the-art high-k/metal gate CMOS technology with the unique capability of independent backgate control for nFETs and pFETs, which is promising for sub-22 nm scaling down.展开更多
文摘Properties of GaAs single crystals grown at low temperatures by molecular beam epitaxy (LTMBE GaAs) have been studied. The results show that excessive arsenic atoms of about 1020 cm?3 exist in LTMBE GaAs in the form of arsenic interstitial couples, and cause the dilation in lattice parameter of LTMBE GaAs. The arsenic interstitial couples will be decomposed, and the excessive arsenic atoms will precipitate during the annealing above 300°C. Arsenic precipitates accumulate in the junctions of epilayers with the increase in the temperature of annealing. The depletion regions caused by arsenic precipitates overlap each other in LTMBE GaAs, taking on the character of high resistivity, and the effects of backgating or sidegating are effectively restrained.
基金Project supported by the National Sciences and Technology Major Project 02
文摘We propose a novel backgate sandwich nanowire MOSFET （SNFET）, which offers the advantages of ETSOI （dynamic backgate voltage controllability） and nanowire FETs （good short channel effect）. A backgate is used for threshold voltage （Vt） control of the SNFET. Compared with a backgate FinFET with a punch-through stop layer （PTSL）, the SNFET possesses improved device performance. 3D device simulations indicate that the SNFET has a three times larger overdrive current, a -75% smaller off leakage current, and reduced subthreshold swing （SS） and DIBL than those of a backgate FinFET when the nanowire （NW） and the fin are of equal width. A new process flow to fabricate the backgate SNFET is also proposed in this work. Our analytical model suggests that Vt control by the backgate can be attributed to the capacitances formed by the frontgate, NW, and backgate. The SNFET devices are compatible with the latest state-of-the-art high-k/metal gate CMOS technology with the unique capability of independent backgate control for nFETs and pFETs, which is promising for sub-22 nm scaling down.
