In this study,we present the development of self-aligned p-channel Ga N back gate injection transistors(SA-BGITs)that exhibit a high ON-state current.This achievement is primarily attributed to the conductivity modula...In this study,we present the development of self-aligned p-channel Ga N back gate injection transistors(SA-BGITs)that exhibit a high ON-state current.This achievement is primarily attributed to the conductivity modulation effect of the 2-D electron gas(2DEG,the back gate)beneath the 2-D hole gas(2DHG)channel.SA-BGITs with a gate length of 1μm have achieved an impressive peak drain current(I_(D,MAX))of 9.9 m A/mm.The fabricated SA-BGITs also possess a threshold voltage of 0.15 V,an exceptionally minimal threshold hysteresis of 0.2 V,a high switching ratio of 10~7,and a reduced ON-resistance(RON)of 548Ω·mm.Additionally,the SA-BGITs exhibit a steep sub-threshold swing(SS)of 173 mV/dec,further highlighting their suitability for integration into Ga N logic circuits.展开更多
Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nm...Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.展开更多
The effects of back gate bias(BGEs) on radio-frequency(RF) performances in PD SOI n MOSFETs are presented in this paper. Floating body(FB) device, T-gate body-contact(TB) device, and tunnel diode body-contact(TDBC) de...The effects of back gate bias(BGEs) on radio-frequency(RF) performances in PD SOI n MOSFETs are presented in this paper. Floating body(FB) device, T-gate body-contact(TB) device, and tunnel diode body-contact(TDBC) device, of which the supply voltages are all 1.2 V, are compared under different back gate biases by different figures of merit, such as cut-off frequency( fT), maximum frequency of oscillation( fmax), etc. Because of the lack of a back gate conducting channel, the drain conductance(gd) of TDBC transistor shows a smaller degradation than those of the others, and the trans-conductance(gm) of TDBC is almost independent of back gate bias. The values of fT of TDBC are also kept nearly constant under different back gate biases. However, RF performances of FB and TB each show a significant degradation when the back gate bias is larger than ～ 20 V. The results indicate that TDBC structures could effectively improve the back gate bias in RF performance.展开更多
The mechanism of improving the TID radiation hardened ability of partially depleted silicon-oninsulator（SOI） devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps intro...The mechanism of improving the TID radiation hardened ability of partially depleted silicon-oninsulator（SOI） devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps introduced in Si O2 near back Si O2/Si interface by phosphorus ions implantation can offset positive trapped charges near the back-gate interface. The implanted high concentration phosphorus ions can greatly reduce the back-gate effect of a partially depleted SOI NMOS device, and anti-total-dose radiation ability can reach the level of 1 Mrad（Si） for experimental devices.展开更多
The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hystere...The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.展开更多
A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in th...A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.展开更多
A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechani...A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate（AG） and back-side etching（BE）. The extended gate consists of a P– region and two diodes in series. In the on-state with VGD〉 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping（VLD） and the ＂hot-spot＂ caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.展开更多
We show the fabrication of flexible graphene devices with an embedded backgate. The resistance of these devices can be tuned by changing the strain through the bending of the substrate. These devices can be useful for...We show the fabrication of flexible graphene devices with an embedded backgate. The resistance of these devices can be tuned by changing the strain through the bending of the substrate. These devices can be useful for applications requiring a flexible graphene-based field effect transistor in where the graphene channel is not covered (such as biological or chemical sensors and photo-detectors).展开更多
二硫化钨(WS_(2))属于过渡金属硫族化合物(TMDs)材料,具有较宽的可调带隙(1.3~2.1 e V),缺陷密度相对较低,且有超高的表面积比,可通过外界掺杂或相变处理来改善载流子传输性能,在低功耗场效应晶体管和超灵敏光电探测器等领域有广阔的应...二硫化钨(WS_(2))属于过渡金属硫族化合物(TMDs)材料,具有较宽的可调带隙(1.3~2.1 e V),缺陷密度相对较低,且有超高的表面积比,可通过外界掺杂或相变处理来改善载流子传输性能,在低功耗场效应晶体管和超灵敏光电探测器等领域有广阔的应用前景。采用微机械剥离的方法将多层WS_(2)薄膜转移到氧化铪(HfO2)介质层上,制备出具有高栅控、低功耗的WS_(2)背栅场效应晶体管,通过注入三乙胺(TEA)实现WS_(2)薄膜的表面电子掺杂。实验结果表明,修饰后的多层WS_(2)薄膜的面内振动模式有轻微位移,拉曼特征峰强度变弱,证明三乙胺溶液能有效增加WS_(2)薄膜内的电子浓度;薄膜与金属电极之间的欧姆接触良好,器件的电子迁移率由10.87 cm^(2)·V^(-1)·s^(-1)提升到24.89 cm^(2)·V^(-1)·s^(-1),室温下的电流开关比保持在106,亚阈值摆幅为190.11 m V/dec。结合理论分析TEA对WS_(2)原子薄层的掺杂机理,TEA通过表面电荷转移的方式来增加WS_(2)半导体内的电子浓度,完成WS_(2)背栅场效应晶体管的n型掺杂。器件较高的电流开关比及电子迁移率的提升证明了TEA的表面修饰能有效调控多层WS_(2)晶体管器件的电子传输特性。展开更多
基金supported in part by the National Key Research and Development Program of China under Grant2022YFB3604400in part by the Youth Innovation Promotion Association of Chinese Academy Sciences(CAS)+5 种基金in part by CAS-Croucher Funding Scheme under Grant CAS22801in part by National Natural Science Foundation of China under Grant 62334012,Grant 62074161,Grant 62004213,Grant U20A20208Grant 62304252in part by the Beijing Municipal Science and Technology Commission project under Grant Z201100008420009 and Grant Z211100007921018in part by the University of CASin part by IMECAS-HKUST-Joint Laboratory of Microelectronics。
文摘In this study,we present the development of self-aligned p-channel Ga N back gate injection transistors(SA-BGITs)that exhibit a high ON-state current.This achievement is primarily attributed to the conductivity modulation effect of the 2-D electron gas(2DEG,the back gate)beneath the 2-D hole gas(2DHG)channel.SA-BGITs with a gate length of 1μm have achieved an impressive peak drain current(I_(D,MAX))of 9.9 m A/mm.The fabricated SA-BGITs also possess a threshold voltage of 0.15 V,an exceptionally minimal threshold hysteresis of 0.2 V,a high switching ratio of 10~7,and a reduced ON-resistance(RON)of 548Ω·mm.Additionally,the SA-BGITs exhibit a steep sub-threshold swing(SS)of 173 mV/dec,further highlighting their suitability for integration into Ga N logic circuits.
基金Supported by the National Program on Key Basic Research Project of China under Grant No 2011CBA00607the National Natural Science Foundation of China under Grant Nos 61106089 and 61376097the Zhejiang Provincial Natural Science Foundation of China under Grant No LR14F040001
文摘Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.
文摘The effects of back gate bias(BGEs) on radio-frequency(RF) performances in PD SOI n MOSFETs are presented in this paper. Floating body(FB) device, T-gate body-contact(TB) device, and tunnel diode body-contact(TDBC) device, of which the supply voltages are all 1.2 V, are compared under different back gate biases by different figures of merit, such as cut-off frequency( fT), maximum frequency of oscillation( fmax), etc. Because of the lack of a back gate conducting channel, the drain conductance(gd) of TDBC transistor shows a smaller degradation than those of the others, and the trans-conductance(gm) of TDBC is almost independent of back gate bias. The values of fT of TDBC are also kept nearly constant under different back gate biases. However, RF performances of FB and TB each show a significant degradation when the back gate bias is larger than ～ 20 V. The results indicate that TDBC structures could effectively improve the back gate bias in RF performance.
基金Project supported by the Major Fund for the National Science and Technology Program,China(No.2009ZX02306-04)the Fund of SOI Research and Development Center(No.20106250XXX)
文摘The mechanism of improving the TID radiation hardened ability of partially depleted silicon-oninsulator（SOI） devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps introduced in Si O2 near back Si O2/Si interface by phosphorus ions implantation can offset positive trapped charges near the back-gate interface. The implanted high concentration phosphorus ions can greatly reduce the back-gate effect of a partially depleted SOI NMOS device, and anti-total-dose radiation ability can reach the level of 1 Mrad（Si） for experimental devices.
基金Project supported by the TCAD Simulation and SPICE Modeling of 0.13μm SOI Technology,China (Grant No. 2009ZX02306-002)
文摘The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.
文摘A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61176069 and 61376079)
文摘A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate（AG） and back-side etching（BE）. The extended gate consists of a P– region and two diodes in series. In the on-state with VGD〉 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping（VLD） and the ＂hot-spot＂ caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.
文摘We show the fabrication of flexible graphene devices with an embedded backgate. The resistance of these devices can be tuned by changing the strain through the bending of the substrate. These devices can be useful for applications requiring a flexible graphene-based field effect transistor in where the graphene channel is not covered (such as biological or chemical sensors and photo-detectors).
文摘二硫化钨(WS_(2))属于过渡金属硫族化合物(TMDs)材料,具有较宽的可调带隙(1.3~2.1 e V),缺陷密度相对较低,且有超高的表面积比,可通过外界掺杂或相变处理来改善载流子传输性能,在低功耗场效应晶体管和超灵敏光电探测器等领域有广阔的应用前景。采用微机械剥离的方法将多层WS_(2)薄膜转移到氧化铪(HfO2)介质层上,制备出具有高栅控、低功耗的WS_(2)背栅场效应晶体管,通过注入三乙胺(TEA)实现WS_(2)薄膜的表面电子掺杂。实验结果表明,修饰后的多层WS_(2)薄膜的面内振动模式有轻微位移,拉曼特征峰强度变弱,证明三乙胺溶液能有效增加WS_(2)薄膜内的电子浓度;薄膜与金属电极之间的欧姆接触良好,器件的电子迁移率由10.87 cm^(2)·V^(-1)·s^(-1)提升到24.89 cm^(2)·V^(-1)·s^(-1),室温下的电流开关比保持在106,亚阈值摆幅为190.11 m V/dec。结合理论分析TEA对WS_(2)原子薄层的掺杂机理,TEA通过表面电荷转移的方式来增加WS_(2)半导体内的电子浓度,完成WS_(2)背栅场效应晶体管的n型掺杂。器件较高的电流开关比及电子迁移率的提升证明了TEA的表面修饰能有效调控多层WS_(2)晶体管器件的电子传输特性。
