In this paper, a very low-offset continuous time amplifier has been presented. It has the fully differential structure and uses an Auto-zeroed offset stabilization technique. This structure consists of two phases in w...In this paper, a very low-offset continuous time amplifier has been presented. It has the fully differential structure and uses an Auto-zeroed offset stabilization technique. This structure consists of two phases in which the offset value is sampled in the first phase and then subtracted from the signal in the second phase. In order to maintain the continuous time topology, the amplifier uses two paths called main-path and sub-path where the main-path is never disconnected from the signal path and as a result the structure will be continuous time. The amplifier is designed to have a total amount of power dissipation about 3 mW in the standard 0.35 μm CMOS process. Furthermore, the proposed Opamp has an offset value lower than 1 μV at a 2.5 kHz Auto-zeroing frequency, unity gain frequency of 6.14 MHz and phase margin of 78.6° with 50 pF loads.展开更多
Thispaperpresentsasingle-ended8-channel 10-bit200kS/s 607 #W synchronous successiveapproxi- mation register （SAR） analog-to-digital converter （ADC） using HLMC 55 nm low leakage （LL） CMOS technology with a 3.3 V/...Thispaperpresentsasingle-ended8-channel 10-bit200kS/s 607 #W synchronous successiveapproxi- mation register （SAR） analog-to-digital converter （ADC） using HLMC 55 nm low leakage （LL） CMOS technology with a 3.3 V/1.2 V supply voltage. In conventional binary-encoded SAR ADCs the total capacitance grows expo- nentially with resolution. In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV. The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167 × 87 μm2. It shows a sampling rate of 200 kS/s and low power dissipation of 607/μW operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage. At the input frequency of 10 kHz the signal-to-noise-and- distortion ratio （SNDR） is 60.1 dB and the spurious-free dynamic range （SFDR） is 68.1 dB. The measured DNL is ±0.37/-0.06 LSB and INL is ±0.58/-0.22 LSB.展开更多
This paper presents a high precision CMOS opamp suitable for ISFET readout. The opamp is tailored to provide a constant bias condition for ISFET as part of the readout circuits and,hence,is compatible for single chip ...This paper presents a high precision CMOS opamp suitable for ISFET readout. The opamp is tailored to provide a constant bias condition for ISFET as part of the readout circuits and,hence,is compatible for single chip integration with the sensor. A continuous time auto-zero stabilization technique is studied and employed, with the aim of suppressing the low frequency noises, including the offset voltage, 1/f noise, and temperature drift. The design is based on a 0.35μm CMOS process. With a 3.3V power supply,it maintains a DC open loop gain of more than 100dB and an offset voltage of around 11μV,while the overall power dissipation is only 1.48mW. With this opamp, a pH microsensor is constructed, of which the functionality is verified by experimental tests.展开更多
本文介绍了一种基于开关电容的带隙基准芯片电路.本文巧妙地利用电容和开关的模拟电阻,实现了静态电流小,温度系数好的开关型基准电压.同时运用自动调零技术,克服了线性基准的失调缺陷,消除了运放的失调电压,提高了输出电压的失调精度....本文介绍了一种基于开关电容的带隙基准芯片电路.本文巧妙地利用电容和开关的模拟电阻,实现了静态电流小,温度系数好的开关型基准电压.同时运用自动调零技术,克服了线性基准的失调缺陷,消除了运放的失调电压,提高了输出电压的失调精度.电路在0.5μm VIS CMOS工艺下实现,温度系数29×10-6V/℃,20mV输入失调电压下的电压漂移仅为0.4mV.展开更多
文摘In this paper, a very low-offset continuous time amplifier has been presented. It has the fully differential structure and uses an Auto-zeroed offset stabilization technique. This structure consists of two phases in which the offset value is sampled in the first phase and then subtracted from the signal in the second phase. In order to maintain the continuous time topology, the amplifier uses two paths called main-path and sub-path where the main-path is never disconnected from the signal path and as a result the structure will be continuous time. The amplifier is designed to have a total amount of power dissipation about 3 mW in the standard 0.35 μm CMOS process. Furthermore, the proposed Opamp has an offset value lower than 1 μV at a 2.5 kHz Auto-zeroing frequency, unity gain frequency of 6.14 MHz and phase margin of 78.6° with 50 pF loads.
基金Project supported by the National Science and Technology Support Program of China(No.2012BAI13B07)the National Science and Technology Major Project of China(No.2012ZX03001020-003)
文摘Thispaperpresentsasingle-ended8-channel 10-bit200kS/s 607 #W synchronous successiveapproxi- mation register （SAR） analog-to-digital converter （ADC） using HLMC 55 nm low leakage （LL） CMOS technology with a 3.3 V/1.2 V supply voltage. In conventional binary-encoded SAR ADCs the total capacitance grows expo- nentially with resolution. In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV. The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167 × 87 μm2. It shows a sampling rate of 200 kS/s and low power dissipation of 607/μW operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage. At the input frequency of 10 kHz the signal-to-noise-and- distortion ratio （SNDR） is 60.1 dB and the spurious-free dynamic range （SFDR） is 68.1 dB. The measured DNL is ±0.37/-0.06 LSB and INL is ±0.58/-0.22 LSB.
文摘This paper presents a high precision CMOS opamp suitable for ISFET readout. The opamp is tailored to provide a constant bias condition for ISFET as part of the readout circuits and,hence,is compatible for single chip integration with the sensor. A continuous time auto-zero stabilization technique is studied and employed, with the aim of suppressing the low frequency noises, including the offset voltage, 1/f noise, and temperature drift. The design is based on a 0.35μm CMOS process. With a 3.3V power supply,it maintains a DC open loop gain of more than 100dB and an offset voltage of around 11μV,while the overall power dissipation is only 1.48mW. With this opamp, a pH microsensor is constructed, of which the functionality is verified by experimental tests.
文摘本文介绍了一种基于开关电容的带隙基准芯片电路.本文巧妙地利用电容和开关的模拟电阻,实现了静态电流小,温度系数好的开关型基准电压.同时运用自动调零技术,克服了线性基准的失调缺陷,消除了运放的失调电压,提高了输出电压的失调精度.电路在0.5μm VIS CMOS工艺下实现,温度系数29×10-6V/℃,20mV输入失调电压下的电压漂移仅为0.4mV.
