High precision and large dynamic range measurement ave required in the readout systems for the Water Cherenkov Detector Array （WCDA） in the Large High Altitude Air Shower Observatory （LHAASO）. This paper presents ...High precision and large dynamic range measurement ave required in the readout systems for the Water Cherenkov Detector Array （WCDA） in the Large High Altitude Air Shower Observatory （LHAASO）. This paper presents a prototype of a 12-bit 40 MSPS Analog-to-Digital Converter （ADC） Application Specific Integrated Circuit （ASIC） designed for the readout of the LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on a power-efficient Successive Approximation Register （SAR） architecture, which incorporates key parts such as a Capacitive Digital-to-Analog Converter （CDAC）, dynamic compavator and asyn- chronous SAR control logic. The simulation results indicate that the Effective Number Of Bits （ENOB） with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA.展开更多
基金Supported by Knowledge Innovation Program of the Chinese Academy of Sciences(KJCX2-YW-N27)CAS Center for Excellence in Particle Physics(CCEPP)
文摘High precision and large dynamic range measurement ave required in the readout systems for the Water Cherenkov Detector Array （WCDA） in the Large High Altitude Air Shower Observatory （LHAASO）. This paper presents a prototype of a 12-bit 40 MSPS Analog-to-Digital Converter （ADC） Application Specific Integrated Circuit （ASIC） designed for the readout of the LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on a power-efficient Successive Approximation Register （SAR） architecture, which incorporates key parts such as a Capacitive Digital-to-Analog Converter （CDAC）, dynamic compavator and asyn- chronous SAR control logic. The simulation results indicate that the Effective Number Of Bits （ENOB） with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA.
