To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of ...To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a collocation table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized(reduced) by 85.8% on average compared with the Versatile Place and Route(VPR) timing-driven routing algorithm, while the run-time is only increased by 15.02% on average.展开更多
An optical routing-switching technology based on optical switch array is proposed.The characteristics of the blocking and nonblocking networks are analyzed and compared,odd-even sorting network is used to realize opti...An optical routing-switching technology based on optical switch array is proposed.The characteristics of the blocking and nonblocking networks are analyzed and compared,odd-even sorting network is used to realize optical routing-switching,relative routing-switching protocol is designed.Simulation test under load shows that it can reduce a blocking effectively and enhance an efficiency of switching.Further,it can transfer the processing and switching within parallel computer from electric domain to optical domain. It can make parallel computer coordinating computing and processing at much more higher speed, storing and transmitting even more efficiently.展开更多
In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ...In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.展开更多
An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv...An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.展开更多
ABC95 array computer is an conflict free access array computer designed with FPGA based circuit partition and circuit integration. FPGA capacity and number of pins are used to judge the design quality. Experimental re...ABC95 array computer is an conflict free access array computer designed with FPGA based circuit partition and circuit integration. FPGA capacity and number of pins are used to judge the design quality. Experimental results show these methods are very useful for design of ABC95 array computer.展开更多
A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a ph...A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication.展开更多
With the continuous evolution of electronic technology,field-programmable gate array(FPGA)has demonstrated significant advantages in the realm of signal acquisition and processing,and signal acquisition plays a pivota...With the continuous evolution of electronic technology,field-programmable gate array(FPGA)has demonstrated significant advantages in the realm of signal acquisition and processing,and signal acquisition plays a pivotal role in the practical applications of laser gyros.By analysis of the output signals from a laser gyro and an accelerometer,this paper presents a circuit design for signal acquisition of the laser gyro based on domestic devices.The design incorporates a finite impulse response(FIR)filter to process the gyro signal and employs a small-volume,impact-resistant quartz flexible accelerometer for signal aquisition.Simulation results demonstrate that the errors in X,Y,and Z axes fall within acceptable ranges while meeting filtering requirements.The use of FPGA for signal acquisition and preprocessing enhances configuration flexibility,which provides an idea and method for optimizing performance and processing signals in laser gyro applications.展开更多
A new hybrid FPGA architecture is proposed. The logic tile,which consists of a logic cluster and related connection boxes （CBs）, can be configured as either programmable logic arrays （PLAs） or look-up tables （LUT...A new hybrid FPGA architecture is proposed. The logic tile,which consists of a logic cluster and related connection boxes （CBs）, can be configured as either programmable logic arrays （PLAs） or look-up tables （LUTs）, This architecture can be classified as an AND-LUT array. PLAs are suitable for the implementation of high fan-in logic circuits, while LUTs are used to implement low fan-in logic circuits. As a result, the proposed hybrid FPGA architecture （HFA） is more flexible to improve logic density. Experiments based on MCNC benchmark circuits were performed in both the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption. Preliminary results indicate that on average, the area is reduced by 46% using the new hybrid architecture.展开更多
基金Supported by National High Technology Research and Develop Program of China(No.2012AA012301)the CAS/SAFEA International Partnership Program for Creative Research Teams
文摘To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a collocation table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized(reduced) by 85.8% on average compared with the Versatile Place and Route(VPR) timing-driven routing algorithm, while the run-time is only increased by 15.02% on average.
文摘An optical routing-switching technology based on optical switch array is proposed.The characteristics of the blocking and nonblocking networks are analyzed and compared,odd-even sorting network is used to realize optical routing-switching,relative routing-switching protocol is designed.Simulation test under load shows that it can reduce a blocking effectively and enhance an efficiency of switching.Further,it can transfer the processing and switching within parallel computer from electric domain to optical domain. It can make parallel computer coordinating computing and processing at much more higher speed, storing and transmitting even more efficiently.
基金Science &Technology Plan Foundation of Hunan Province,China(No.2010F3102)Science Research Foundation of Hunan Province,China(No.08C392)
文摘In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.
文摘An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.
文摘ABC95 array computer is an conflict free access array computer designed with FPGA based circuit partition and circuit integration. FPGA capacity and number of pins are used to judge the design quality. Experimental results show these methods are very useful for design of ABC95 array computer.
基金The National Natural Science Foundation of China(No.62401168,62401139,62401170)China Postdoctoral Science Foundation(No.2023MD744197)+2 种基金Postdoctoral Fellowship Program of CPSF(No.GZC20230631)Project for Enhancing Young and Middle-aged Teacher’s Research Basis Ability in Colleges of Guangxi(No.2023KY0218)Guangxi Key Laboratory Foundation of Optoelectronic Information Processing(No.GD23102)。
文摘A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication.
文摘With the continuous evolution of electronic technology,field-programmable gate array(FPGA)has demonstrated significant advantages in the realm of signal acquisition and processing,and signal acquisition plays a pivotal role in the practical applications of laser gyros.By analysis of the output signals from a laser gyro and an accelerometer,this paper presents a circuit design for signal acquisition of the laser gyro based on domestic devices.The design incorporates a finite impulse response(FIR)filter to process the gyro signal and employs a small-volume,impact-resistant quartz flexible accelerometer for signal aquisition.Simulation results demonstrate that the errors in X,Y,and Z axes fall within acceptable ranges while meeting filtering requirements.The use of FPGA for signal acquisition and preprocessing enhances configuration flexibility,which provides an idea and method for optimizing performance and processing signals in laser gyro applications.
文摘A new hybrid FPGA architecture is proposed. The logic tile,which consists of a logic cluster and related connection boxes （CBs）, can be configured as either programmable logic arrays （PLAs） or look-up tables （LUTs）, This architecture can be classified as an AND-LUT array. PLAs are suitable for the implementation of high fan-in logic circuits, while LUTs are used to implement low fan-in logic circuits. As a result, the proposed hybrid FPGA architecture （HFA） is more flexible to improve logic density. Experiments based on MCNC benchmark circuits were performed in both the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption. Preliminary results indicate that on average, the area is reduced by 46% using the new hybrid architecture.
