To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（Σ...To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.展开更多
In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchao...In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchaos. The hyperchaotic nature is verified theoretically by using the bifurcation analysis and demonstrated experimentally by the implementation of an analogue electronic circuit. Moreover, the Field Programmable Gate Array （FPGA） technology is applied to implementing a continuous system in a digital form by using a chip of Altera Cyclone II EP2C35F484C8. The digital sequence generated from the FPGA device is observed in our experimental setup.展开更多
In this paper, the structure of a new chaotic bitwise dynamical system （CBDS） is described. Compared to our previous research work, it uses various random bitwise operations instead of only one. The chaotic behavior...In this paper, the structure of a new chaotic bitwise dynamical system （CBDS） is described. Compared to our previous research work, it uses various random bitwise operations instead of only one. The chaotic behavior of CBDS is mathemat- ically proven according to the Devaney＇s definition, and its statistical properties are verified both for uniformity and by a comprehensive, reputed and stringent battery of tests called TestU01. Furthermore, a systematic methodology developing the parallel computations is proposed for FPGA platform-based realization of this CBDS. Experiments finally validate the proposed systematic methodology.展开更多
This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diago...This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.展开更多
随着数字音源的普及,数模转换器(Digital to Analog Converter, DAC)成为音频设备中不可或缺的元件,其精度往往决定着整个系统的信号保真度。基于此,利用噪声整形技术对用于高精度音频DAC的Sigma-Delta调制器进行设计和现场可编程门阵列...随着数字音源的普及,数模转换器(Digital to Analog Converter, DAC)成为音频设备中不可或缺的元件,其精度往往决定着整个系统的信号保真度。基于此,利用噪声整形技术对用于高精度音频DAC的Sigma-Delta调制器进行设计和现场可编程门阵列(Field Programmable Gate Array, FPGA)实现。通过搭建测试系统,测试结果表明,所设计的Sigma-Delta调制器在输入信号为1 411.2 kHz采样频率、1 kHz频率、0 dBFS(Full Scale)幅度的正弦信号条件下,其输出信噪比(Signal to Noise Ratio, SNR)可达107.4 dB;当输入信号频率在音频频带内时(输入信号幅度为0dBFS),其输出SNR稳定保持在104 dB以上;并可用于WAV音乐播放器中。展开更多
This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcatio...This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcation diagram, basic dynamics have been analyzed. The hardware implementation of the system is based on Field Programmable Gate Array (FPGA). It is shown that the experimental results are identical with numerical simulations, and the chaotic trajectories are much more complex.展开更多
An improved heterogeneous dual memristive circuit(DMC)is proposed based on Chua's circuit,which shows good symmetry and multistablility.For the difficulty in controlling the initial conditions,which restricts the ...An improved heterogeneous dual memristive circuit(DMC)is proposed based on Chua's circuit,which shows good symmetry and multistablility.For the difficulty in controlling the initial conditions,which restricts the engineering applications,the 3 rd-order model(3 OM)in flux-charge domain is derived from the 5 th-order model(5 OM)in volt-ampere domain by using the flux-charge analysis method(FCAM).The consistence of symmetry and multistability before and after dimensionality decreasing is meticulously investigated via bifurcation diagram,Lyapunov exponents,and especially attraction basins.The comparative analysis validates the effectiveness of reduction model and improves the controllability of the circuit.To avoid the noise in the analog circuit,a field-programmable gate array(FPGA)is utilized to realize the reduction model,which is rarely reported and valuable for relevant research and application.展开更多
Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is co...Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption.展开更多
A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm ...A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.展开更多
It is necessary to know the status of adhesion conditions between wheel and rail for efficient accelerating and decelerating of railroad vehicle.The proper estimation of adhesion conditions and their real-time impleme...It is necessary to know the status of adhesion conditions between wheel and rail for efficient accelerating and decelerating of railroad vehicle.The proper estimation of adhesion conditions and their real-time implementation is considered a challenge for scholars.In this paper,the development of simulation model of extended Kalman filter(EKF)in MATLAB/Simulink is presented to estimate various railway wheelset parameters in different contact conditions of track.Due to concurrent in nature,the Xilinx®System-on-Chip Zynq Field Programmable Gate Array(FPGA)device is chosen to check the onboard estimation ofwheel-rail interaction parameters by using the National Instruments(NI)myRIO®development board.The NImyRIO®development board is flexible to deal with nonlinearities,uncertain changes,and fastchanging dynamics in real-time occurring in wheel-rail contact conditions during vehicle operation.The simulated dataset of the railway nonlinear wheelsetmodel is tested on FPGA-based EKF with different track conditions and with accelerating and decelerating operations of the vehicle.The proposed model-based estimation of railway wheelset parameters is synthesized on FPGA and its simulation is carried out for functional verification on FPGA.The obtained simulation results are aligned with the simulation results obtained through MATLAB.To the best of our knowledge,this is the first time study that presents the implementation of a model-based estimation of railway wheelset parameters on FPGA and its functional verification.The functional behavior of the FPGA-based estimator shows that these results are the addition of current knowledge in the field of the railway.展开更多
In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ...In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.展开更多
A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC...A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.展开更多
In this paper, a high-performance and low-complexity luminance transient improvement （LTI） algorithm is proposed and efficiently implemented on field programmable gate army （FPGA） devices, which can be widely used...In this paper, a high-performance and low-complexity luminance transient improvement （LTI） algorithm is proposed and efficiently implemented on field programmable gate army （FPGA） devices, which can be widely used to enhance the sharpness of digital video. The proposed algorithm generates the cor- rection signal by using the difference of the outputs of two Gaussian filters with different variances, and then modulates the correction signal adaptively according to the local contrast information of video frames. A 2-D min/max nonlinear filter is employed to suppress overshoots around edges. The proposed algorithm is thoroughly confirmed by experiments and compared with other algorithms on irrkages, which produces steeper edges and better visual quality while suppressing noise and artifacts. And the hardware architecture suitable for FPGA implementation is optimized based on the property of the algorithm and proves to be effective and efficient in many respects, such as resource consumption, performance and reconfigura- bility. The specific implementation details on both Xilinx and Ahera FPGA devices are also described in this paper.展开更多
This paper proposes the fractal patterns classifier for multiple cardiac arrhythmias on field-programmable gate array (FPGA) device. Fractal dimension transformation (FDT) is employed to adjoin the fractal features of...This paper proposes the fractal patterns classifier for multiple cardiac arrhythmias on field-programmable gate array (FPGA) device. Fractal dimension transformation (FDT) is employed to adjoin the fractal features of QRS-complex, including the supraventricular ectopic beat, bundle branch ectopic beat, and ventricular ectopic beat. FDT with fractal dimension (FD) is addressed for constructing various symptomatic patterns, which can produce family functions and enhance features, making clear differences between normal and unhealthy subjects. The probabilistic neural network (PNN) is proposed for recognizing multiple cardiac arrhythmias. Numerical experiments verify the efficiency and higher accuracy with the software simulation in order to formulate the mathematical model logical circuits. FDT results in data self-similarity for the same arrhythmia category, the number of dataset requirement and PNN architecture can be reduced. Its simplified model can be easily embedded in the FPGA chip. The prototype classifier is tested using the MIT-BIH arrhythmia database, and the tests reveal its practicality for monitoring ECG signals.展开更多
An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv...An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.展开更多
ABC95 array computer is an conflict free access array computer designed with FPGA based circuit partition and circuit integration. FPGA capacity and number of pins are used to judge the design quality. Experimental re...ABC95 array computer is an conflict free access array computer designed with FPGA based circuit partition and circuit integration. FPGA capacity and number of pins are used to judge the design quality. Experimental results show these methods are very useful for design of ABC95 array computer.展开更多
In this paper,a fast-speed and real-time online rail inspection method based on half-cycle orthogonal power demodulation algorithm is proposed.For this method,the power characters of de-tection signal which represent ...In this paper,a fast-speed and real-time online rail inspection method based on half-cycle orthogonal power demodulation algorithm is proposed.For this method,the power characters of de-tection signal which represent the degree of rail track can be calculated using only half-cycle detec-tion signal because of the symmetry characteristic of detected sine signal and reference signal.The theoretical analysis,simulation results and experiment results show that the demodulation preci-sion of proposed method is almost equal to fast Fourier transform(FFT)demodulation method and orthogonal demodulation method,but has high demodulation efficiency and less FPGA resources cost.A high-speed experiment system based on three coils structured sensor is built for rail inspec-tion experiment at a moving speed of 200 km/h.The experiment results show that proposed meth-od is more effective for rail inspection and the time resolution of proposed method is double of clas-sic method that based on FFT and orthogonal.展开更多
基金The National Natural Science Foundation of China (No.60576028)the Natural Science Foundation of Higher Education Institutions of Jiangsu Province(No.11KJB510004)
文摘To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.
基金Project supported by the Natural Science Foundation of Zhejiang Province, China (Grant No Y105175) the Science investigation Foundation of Hangzhou Dianzi University, China (Grant No KYS051505010)
文摘In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchaos. The hyperchaotic nature is verified theoretically by using the bifurcation analysis and demonstrated experimentally by the implementation of an analogue electronic circuit. Moreover, the Field Programmable Gate Array （FPGA） technology is applied to implementing a continuous system in a digital form by using a chip of Altera Cyclone II EP2C35F484C8. The digital sequence generated from the FPGA device is observed in our experimental setup.
基金Project supported by China Postdoctoral Science Foundation(Grant No.2014M552175)the Scientific Research Foundation for the Returned Overseas Chinese Scholars,Chinese Education Ministry+1 种基金the National Natural Science Foundation of China(Grant No.61172023)the Specialized Research Foundation of Doctoral Subjects of Chinese Education Ministry(Grant No.20114420110003)
文摘In this paper, the structure of a new chaotic bitwise dynamical system （CBDS） is described. Compared to our previous research work, it uses various random bitwise operations instead of only one. The chaotic behavior of CBDS is mathemat- ically proven according to the Devaney＇s definition, and its statistical properties are verified both for uniformity and by a comprehensive, reputed and stringent battery of tests called TestU01. Furthermore, a systematic methodology developing the parallel computations is proposed for FPGA platform-based realization of this CBDS. Experiments finally validate the proposed systematic methodology.
基金supported by the National Natural Science Foundation of China(11705191)the Anhui Provincial Natural Science Foundation(1808085QF180)the Natural Science Foundation of Shanghai(18ZR1443600)
文摘This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.
文摘This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcation diagram, basic dynamics have been analyzed. The hardware implementation of the system is based on Field Programmable Gate Array (FPGA). It is shown that the experimental results are identical with numerical simulations, and the chaotic trajectories are much more complex.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61971228 and 61871230)the Natural Science Foundations of Jiangsu Higher Education Institutions,China(Grant No.19KJB520042)the Postgraduate Research&Practice Innovation Program of Jiangsu Province,China(Grant No.SJCX210564)。
文摘An improved heterogeneous dual memristive circuit(DMC)is proposed based on Chua's circuit,which shows good symmetry and multistablility.For the difficulty in controlling the initial conditions,which restricts the engineering applications,the 3 rd-order model(3 OM)in flux-charge domain is derived from the 5 th-order model(5 OM)in volt-ampere domain by using the flux-charge analysis method(FCAM).The consistence of symmetry and multistability before and after dimensionality decreasing is meticulously investigated via bifurcation diagram,Lyapunov exponents,and especially attraction basins.The comparative analysis validates the effectiveness of reduction model and improves the controllability of the circuit.To avoid the noise in the analog circuit,a field-programmable gate array(FPGA)is utilized to realize the reduction model,which is rarely reported and valuable for relevant research and application.
基金Project supported by the Natural Science Foundation of Tianjin,China(Grant No.18JCYBJC87700)the Natural Science Foundation of China(Grant No.61603274)。
文摘Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption.
文摘A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.
文摘It is necessary to know the status of adhesion conditions between wheel and rail for efficient accelerating and decelerating of railroad vehicle.The proper estimation of adhesion conditions and their real-time implementation is considered a challenge for scholars.In this paper,the development of simulation model of extended Kalman filter(EKF)in MATLAB/Simulink is presented to estimate various railway wheelset parameters in different contact conditions of track.Due to concurrent in nature,the Xilinx®System-on-Chip Zynq Field Programmable Gate Array(FPGA)device is chosen to check the onboard estimation ofwheel-rail interaction parameters by using the National Instruments(NI)myRIO®development board.The NImyRIO®development board is flexible to deal with nonlinearities,uncertain changes,and fastchanging dynamics in real-time occurring in wheel-rail contact conditions during vehicle operation.The simulated dataset of the railway nonlinear wheelsetmodel is tested on FPGA-based EKF with different track conditions and with accelerating and decelerating operations of the vehicle.The proposed model-based estimation of railway wheelset parameters is synthesized on FPGA and its simulation is carried out for functional verification on FPGA.The obtained simulation results are aligned with the simulation results obtained through MATLAB.To the best of our knowledge,this is the first time study that presents the implementation of a model-based estimation of railway wheelset parameters on FPGA and its functional verification.The functional behavior of the FPGA-based estimator shows that these results are the addition of current knowledge in the field of the railway.
基金Science &Technology Plan Foundation of Hunan Province,China(No.2010F3102)Science Research Foundation of Hunan Province,China(No.08C392)
文摘In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.
基金Supported by the Ministerial Level Advanced Research Foundation (SP240012)
文摘A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.
基金Supported by the National Science and Technology Support Projects Funded by Ministry of Science & Technology of China (No. 2006BAK07B04)
文摘In this paper, a high-performance and low-complexity luminance transient improvement （LTI） algorithm is proposed and efficiently implemented on field programmable gate army （FPGA） devices, which can be widely used to enhance the sharpness of digital video. The proposed algorithm generates the cor- rection signal by using the difference of the outputs of two Gaussian filters with different variances, and then modulates the correction signal adaptively according to the local contrast information of video frames. A 2-D min/max nonlinear filter is employed to suppress overshoots around edges. The proposed algorithm is thoroughly confirmed by experiments and compared with other algorithms on irrkages, which produces steeper edges and better visual quality while suppressing noise and artifacts. And the hardware architecture suitable for FPGA implementation is optimized based on the property of the algorithm and proves to be effective and efficient in many respects, such as resource consumption, performance and reconfigura- bility. The specific implementation details on both Xilinx and Ahera FPGA devices are also described in this paper.
文摘This paper proposes the fractal patterns classifier for multiple cardiac arrhythmias on field-programmable gate array (FPGA) device. Fractal dimension transformation (FDT) is employed to adjoin the fractal features of QRS-complex, including the supraventricular ectopic beat, bundle branch ectopic beat, and ventricular ectopic beat. FDT with fractal dimension (FD) is addressed for constructing various symptomatic patterns, which can produce family functions and enhance features, making clear differences between normal and unhealthy subjects. The probabilistic neural network (PNN) is proposed for recognizing multiple cardiac arrhythmias. Numerical experiments verify the efficiency and higher accuracy with the software simulation in order to formulate the mathematical model logical circuits. FDT results in data self-similarity for the same arrhythmia category, the number of dataset requirement and PNN architecture can be reduced. Its simplified model can be easily embedded in the FPGA chip. The prototype classifier is tested using the MIT-BIH arrhythmia database, and the tests reveal its practicality for monitoring ECG signals.
文摘An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.
文摘ABC95 array computer is an conflict free access array computer designed with FPGA based circuit partition and circuit integration. FPGA capacity and number of pins are used to judge the design quality. Experimental results show these methods are very useful for design of ABC95 array computer.
基金supported by the National Natural Science Found-ation of China(No.61771041).
文摘In this paper,a fast-speed and real-time online rail inspection method based on half-cycle orthogonal power demodulation algorithm is proposed.For this method,the power characters of de-tection signal which represent the degree of rail track can be calculated using only half-cycle detec-tion signal because of the symmetry characteristic of detected sine signal and reference signal.The theoretical analysis,simulation results and experiment results show that the demodulation preci-sion of proposed method is almost equal to fast Fourier transform(FFT)demodulation method and orthogonal demodulation method,but has high demodulation efficiency and less FPGA resources cost.A high-speed experiment system based on three coils structured sensor is built for rail inspec-tion experiment at a moving speed of 200 km/h.The experiment results show that proposed meth-od is more effective for rail inspection and the time resolution of proposed method is double of clas-sic method that based on FFT and orthogonal.
