This paper presents an ultra-low-power area-efficient non-volatile memory（NVM） in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification（RFID） tags.In the memory cell,a novel low-pow...This paper presents an ultra-low-power area-efficient non-volatile memory（NVM） in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification（RFID） tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm^2 and 0.12 mm^2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of （268 kb/s）/（3.0 kb/s）.展开更多
In the recent years,error recovery circuits in optimized data path units are adopted with approximate computing methodology.In this paper the novel multipliers have effective utilization in the newly proposed two diff...In the recent years,error recovery circuits in optimized data path units are adopted with approximate computing methodology.In this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum(ES)and Error free Carry(EC).Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product(PP)compression.The structural arrangement utilizes Dadda structure based PP.Due to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC design.In this,the proposed compression idealogy are more effective in the smallest n columns,and the accurate compressor in the remaining most significant columns.This limits the error in the multiplier output to be not more than 2n for an n X n multiplication.The choice among the proposed compressors is decided based on the significance of the sum and carry signals on the multiplier result.As an enhancement to the proposed multiplier,we introduce two Area Efficient(AE)variants viz.,Proposed-AE(P-AE),and P-AE with Error Recovery(P-AEER).The proposed basic P-AE,and P-AEER designs exhibit 46.7%,52.9%,and 52.7%PDP reduction respectively when compared to an approximate multiplier of minimal error type and are designed with 90nm ASIC technology.The proposed design and their performance validation are done by using Cadence Encounter.The performance evaluations are carried out using cadence encounter with 90nm ASIC technology.The proposed-basic P-AEA and P-AEER designs demonstrate 46.7%,52.9%and 52.7%PDP reduction compared to the minimal error approximate multiplier.The proposed multiplier is implemented in digital image processing which revealed 0.9810 Structural SIMilarity Index(SSIM),to the least,and less than 3%deviation in ECG signal processing application.展开更多
基金supported by the National Key Technology Research and Development Program of the Ministry of Science and Technology of China(No.2012BAH20B02)the National High Technology Research and Development Program of China(No.2012AA012301)the National Science and Technology Major Projects of the Ministry of Science and Technology of China(No.2012ZX03004007-002)
文摘This paper presents an ultra-low-power area-efficient non-volatile memory（NVM） in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification（RFID） tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm^2 and 0.12 mm^2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of （268 kb/s）/（3.0 kb/s）.
文摘In the recent years,error recovery circuits in optimized data path units are adopted with approximate computing methodology.In this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum(ES)and Error free Carry(EC).Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product(PP)compression.The structural arrangement utilizes Dadda structure based PP.Due to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC design.In this,the proposed compression idealogy are more effective in the smallest n columns,and the accurate compressor in the remaining most significant columns.This limits the error in the multiplier output to be not more than 2n for an n X n multiplication.The choice among the proposed compressors is decided based on the significance of the sum and carry signals on the multiplier result.As an enhancement to the proposed multiplier,we introduce two Area Efficient(AE)variants viz.,Proposed-AE(P-AE),and P-AE with Error Recovery(P-AEER).The proposed basic P-AE,and P-AEER designs exhibit 46.7%,52.9%,and 52.7%PDP reduction respectively when compared to an approximate multiplier of minimal error type and are designed with 90nm ASIC technology.The proposed design and their performance validation are done by using Cadence Encounter.The performance evaluations are carried out using cadence encounter with 90nm ASIC technology.The proposed-basic P-AEA and P-AEER designs demonstrate 46.7%,52.9%and 52.7%PDP reduction compared to the minimal error approximate multiplier.The proposed multiplier is implemented in digital image processing which revealed 0.9810 Structural SIMilarity Index(SSIM),to the least,and less than 3%deviation in ECG signal processing application.
