For multi-channel synthetic aperture radar（SAR） systems, since the minimum antenna area constraint is eliminated,wide swath and high resolution SAR image can be achieved.However, the unavoidable array errors, consis...For multi-channel synthetic aperture radar（SAR） systems, since the minimum antenna area constraint is eliminated,wide swath and high resolution SAR image can be achieved.However, the unavoidable array errors, consisting of channel gainphase mismatch and position uncertainty, significantly degrade the performance of such systems. An iteration-free method is proposed to simultaneously estimate position and gain-phase errors.In our research, the steering vectors corresponding to a pair of Doppler bins within the same range bin are studied in terms of their rotational relationships. The method is based on the fact that the rotational matrix only depends on the position errors and the frequency spacing between the paired Doppler bins but is independent of gain-phase error. Upon combining the projection matrices corresponding to the paired Doppler bins, the position errors are directly obtained in terms of extracting the rotational matrix in a least squares framework. The proposed method, when used in conjunction with the self-calibration algorithm, performs stably as well as has less computational load, compared with the conventional methods. Simulations reveal that the proposed method behaves better than the conventional methods even when the signal-to-noise ratio（SNR） is low.展开更多
A new design technique for merging the front-end sample-and-hold amplifier（SHA） into the first multiplying digital-to-analog converter（MDAC） is presented.For reducing the aperture error in the first stage of the p...A new design technique for merging the front-end sample-and-hold amplifier（SHA） into the first multiplying digital-to-analog converter（MDAC） is presented.For reducing the aperture error in the first stage of the pipelined ADC,a symmetrical structure is used in a flash ADC and MDAC.Furthermore,a variable resistor tuning network is placed at the flash input to compensate for different cutoff frequencies of the input impedances of the flash and MDAC.The circuit also has a clear clock phase in the MDAC and separate sampling capacitors in the flash ADC to eliminate the nonlinear charge kickback to the input signal.The proposed circuit,designed using ASMC 0.35-μm BiCMOS technology,occupies an area of 1.4 x 9 mm^2 and is used as the front-end stage in a 14-bit 125-MS/s pipelined ADC.After the trim circuit is enabled,the measured signal-to-noise ratio is improved from 71.5 to 73.6 dB and the spurious free dynamic range is improved from 80.5 to 83.1 dB with a 30.8 MHz input. The maximum input frequency is up to 150 MHz without steep performance degradations.展开更多
基金supported by the Natural Science Basic Research Plan in Shaanxi Province of China(2015JM6278)the China Postdoctoral Science Foundation(2015M582586)the China Academy of Space Technology Innovation Fund
文摘For multi-channel synthetic aperture radar（SAR） systems, since the minimum antenna area constraint is eliminated,wide swath and high resolution SAR image can be achieved.However, the unavoidable array errors, consisting of channel gainphase mismatch and position uncertainty, significantly degrade the performance of such systems. An iteration-free method is proposed to simultaneously estimate position and gain-phase errors.In our research, the steering vectors corresponding to a pair of Doppler bins within the same range bin are studied in terms of their rotational relationships. The method is based on the fact that the rotational matrix only depends on the position errors and the frequency spacing between the paired Doppler bins but is independent of gain-phase error. Upon combining the projection matrices corresponding to the paired Doppler bins, the position errors are directly obtained in terms of extracting the rotational matrix in a least squares framework. The proposed method, when used in conjunction with the self-calibration algorithm, performs stably as well as has less computational load, compared with the conventional methods. Simulations reveal that the proposed method behaves better than the conventional methods even when the signal-to-noise ratio（SNR） is low.
基金supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028,61006028)the National High-Tech R&D Program of China(No.2009AA01Z258)the Shaanxi Special Major Technological Innovation Program(No. 2009ZKC02-11 )
文摘A new design technique for merging the front-end sample-and-hold amplifier（SHA） into the first multiplying digital-to-analog converter（MDAC） is presented.For reducing the aperture error in the first stage of the pipelined ADC,a symmetrical structure is used in a flash ADC and MDAC.Furthermore,a variable resistor tuning network is placed at the flash input to compensate for different cutoff frequencies of the input impedances of the flash and MDAC.The circuit also has a clear clock phase in the MDAC and separate sampling capacitors in the flash ADC to eliminate the nonlinear charge kickback to the input signal.The proposed circuit,designed using ASMC 0.35-μm BiCMOS technology,occupies an area of 1.4 x 9 mm^2 and is used as the front-end stage in a 14-bit 125-MS/s pipelined ADC.After the trim circuit is enabled,the measured signal-to-noise ratio is improved from 71.5 to 73.6 dB and the spurious free dynamic range is improved from 80.5 to 83.1 dB with a 30.8 MHz input. The maximum input frequency is up to 150 MHz without steep performance degradations.
