In this study,a Gaussian Process Regression(GPR)surrogate model coupled with a Bayesian optimization algorithm was employed for the single-objective design optimization of fan-shaped film cooling holes on a concave wa...In this study,a Gaussian Process Regression(GPR)surrogate model coupled with a Bayesian optimization algorithm was employed for the single-objective design optimization of fan-shaped film cooling holes on a concave wall.Fan-shaped holes,commonly used in gas turbines and aerospace applications,flare toward the exit to form a protective cooling film over hot surfaces,enhancing thermal protection compared to cylindrical holes.An initial hole configuration was used to improve adiabatic cooling efficiency.Design variables included the hole injection angle,forward expansion angle,lateral expansion angle,and aperture ratio,while the objective function was the average adiabatic cooling efficiency of the concave wall surface.Optimization was performed at two representative blowing ratios,M=1.0 and M=1.5,using the GPR-based surrogate model to accelerate exploration,with the Bayesian algorithm identifying optimal configurations.Results indicate that the optimized fan-shaped holes increased cooling efficiency by 15.2%and 12.3%at low and high blowing ratios,respectively.Analysis of flow and thermal fields further revealed how the optimized geometry influenced coolant distribution and heat transfer,providing insight into the mechanisms driving the improved cooling performance.展开更多
This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology pa...This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.展开更多
基金supported by the Jiangsu Association for Science and Technology,grant number SKX 0225089the National Natural Science Foundation of China,grant number 52476027.
文摘In this study,a Gaussian Process Regression(GPR)surrogate model coupled with a Bayesian optimization algorithm was employed for the single-objective design optimization of fan-shaped film cooling holes on a concave wall.Fan-shaped holes,commonly used in gas turbines and aerospace applications,flare toward the exit to form a protective cooling film over hot surfaces,enhancing thermal protection compared to cylindrical holes.An initial hole configuration was used to improve adiabatic cooling efficiency.Design variables included the hole injection angle,forward expansion angle,lateral expansion angle,and aperture ratio,while the objective function was the average adiabatic cooling efficiency of the concave wall surface.Optimization was performed at two representative blowing ratios,M=1.0 and M=1.5,using the GPR-based surrogate model to accelerate exploration,with the Bayesian algorithm identifying optimal configurations.Results indicate that the optimized fan-shaped holes increased cooling efficiency by 15.2%and 12.3%at low and high blowing ratios,respectively.Analysis of flow and thermal fields further revealed how the optimized geometry influenced coolant distribution and heat transfer,providing insight into the mechanisms driving the improved cooling performance.
基金supported by the Project SMDP-II,MCIT,Govt.of India
文摘This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.
