A low-power three-stage amplifier for driving large capacitive load is proposed. The feedback path formed by the active-feedback Miller capacitor leads to a high frequency complex-pole but a high Q-value, which signif...A low-power three-stage amplifier for driving large capacitive load is proposed. The feedback path formed by the active-feedback Miller capacitor leads to a high frequency complex-pole but a high Q-value, which significantly deteriorates the stability of the amplifier. The serial RC stage introduced as the second stage output load can optimize the resistor Rz and the capacitor Cz under fixed power and small compensation capacitor Ca, which brings about a suitable Q-value of the complex-pole and the gain-bandwidth product extension of the amplifier. The amplifiers were designed and implemented in a standard 65 nm CMOS process with capacitive loads of 500 p F and 2 n F, respectively. The post-layout simulation results show that the amplifier driving the 500 p F capacitive load can achieve a gain of 113 d B, a phase margin of 50.6° and a gain-bandwidth product of 5.22 MHz while consuming 24 μW from a 1.2 V supply. For the 2 n F capacitive load, the amplifier has a gain of 102 d B, a phase margin of 52.8°, a gain-bandwidth product of 4.41 MHz and a power of 43 μW. The total compensation capacitors are equal to 1.13 p F and 1.03 p F. The better figures-of-merits are 108 750 and 205 113(MHz×p F/m W). The layout areas are 0.064 mm×0.026 mm and 0.063 mm×0.027 mm. Compared with the CFCC scheme, the gainbandwidth product is extended by 1.6 times at CL=500 p F and Ca=1.1 p F.展开更多
A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, wh...A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.展开更多
基金Supported by the Tianjin Science and Technology Project(No.13ZCZDGX02000)
文摘A low-power three-stage amplifier for driving large capacitive load is proposed. The feedback path formed by the active-feedback Miller capacitor leads to a high frequency complex-pole but a high Q-value, which significantly deteriorates the stability of the amplifier. The serial RC stage introduced as the second stage output load can optimize the resistor Rz and the capacitor Cz under fixed power and small compensation capacitor Ca, which brings about a suitable Q-value of the complex-pole and the gain-bandwidth product extension of the amplifier. The amplifiers were designed and implemented in a standard 65 nm CMOS process with capacitive loads of 500 p F and 2 n F, respectively. The post-layout simulation results show that the amplifier driving the 500 p F capacitive load can achieve a gain of 113 d B, a phase margin of 50.6° and a gain-bandwidth product of 5.22 MHz while consuming 24 μW from a 1.2 V supply. For the 2 n F capacitive load, the amplifier has a gain of 102 d B, a phase margin of 52.8°, a gain-bandwidth product of 4.41 MHz and a power of 43 μW. The total compensation capacitors are equal to 1.13 p F and 1.03 p F. The better figures-of-merits are 108 750 and 205 113(MHz×p F/m W). The layout areas are 0.064 mm×0.026 mm and 0.063 mm×0.027 mm. Compared with the CFCC scheme, the gainbandwidth product is extended by 1.6 times at CL=500 p F and Ca=1.1 p F.
文摘A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.
