In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves a...In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves as a cache memory in computers and many portable devices.Carbon nanotubes(CNTs),because of their exceptional transport capabilities,outstanding thermal conductivities,and impressive current handling capacities,have demonstrated great potential as an alternative device to the standard complementary metal-oxide-semiconductor(CMOS).The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology.This paper presents the comprehensive analysis of CMOS&CNTFET based 8T SRAM cell design.Because of the nanoscale size,ballistic transport,and higher carrier mobility of the semiconducting nanotubes in CNTFET,it is integrated into the 8T SRAM cell.The approach incorporates several nonidealities,including the presence of quantum confinement consequences in the peripheral and transverse prescriptions,acoustic and transparent photon diffraction in the region surrounding the channel,as well as the screening effects by parallel CNTs in CNTFETs with multiple CNTs.By incorporating Stanford University CNTFET model in CADENCE(virtuoso)32 nm simulation,we have found that CNTFET SRAM cell is 4 times faster in terms of write/read delay and the write/read power delay product(PDP)value is almost 5 times lower compared to CMOS based SRAM.We have also analyzed the effect of temperature&different tube positions of CNTs on the performance evaluation of the 8T SRAM cell.展开更多
A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applie...A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line（BNBL） provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line（NBL） and boosted bit line（BBL） write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.展开更多
文摘In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves as a cache memory in computers and many portable devices.Carbon nanotubes(CNTs),because of their exceptional transport capabilities,outstanding thermal conductivities,and impressive current handling capacities,have demonstrated great potential as an alternative device to the standard complementary metal-oxide-semiconductor(CMOS).The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology.This paper presents the comprehensive analysis of CMOS&CNTFET based 8T SRAM cell design.Because of the nanoscale size,ballistic transport,and higher carrier mobility of the semiconducting nanotubes in CNTFET,it is integrated into the 8T SRAM cell.The approach incorporates several nonidealities,including the presence of quantum confinement consequences in the peripheral and transverse prescriptions,acoustic and transparent photon diffraction in the region surrounding the channel,as well as the screening effects by parallel CNTs in CNTFETs with multiple CNTs.By incorporating Stanford University CNTFET model in CADENCE(virtuoso)32 nm simulation,we have found that CNTFET SRAM cell is 4 times faster in terms of write/read delay and the write/read power delay product(PDP)value is almost 5 times lower compared to CMOS based SRAM.We have also analyzed the effect of temperature&different tube positions of CNTs on the performance evaluation of the 8T SRAM cell.
文摘A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line（BNBL） provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line（NBL） and boosted bit line（BBL） write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.
