This article deals with two important issues in digital filter implementation： roundoff noise and limit cycles. A novel class of robust state-space realizations, called normal realizations, is derived and characteriz...This article deals with two important issues in digital filter implementation： roundoff noise and limit cycles. A novel class of robust state-space realizations, called normal realizations, is derived and characterized. It is seen that these realizations are free of limit cycles. Another interesting property of the normal realizations is that they yield a minimal error propagation gain. The optimal realization problem, defined as to find those normal realizations that minimize roundoff noise gain, is formulated and solved analytically. A design example is presented to demonstrate the behavior of the optimal normal realizations and to compare them with several well-known digital filter realizations in terms of minimizing the roundoff noise and the error propagation.展开更多
The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system...The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system performance,a modified scheme is presented to decline the resource consumption without too much degradation on the signal to noise ratio（SNR）.Theoretical analysis and numerical results demonstrate that compared to the traditional design,the proposed scheme could save dozens of memory resources.The scheme also includes some selectable parameters to achieve desired performance in various circumstances.Different from previous work in DDCs that concentrates mostly on the structure design,this paper considers special applications such as ultra-low symbol rate receivers.展开更多
The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom...The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.展开更多
ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to ...ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms： Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer4evel （RTL） level as technology-independent reusable IP-cores. They are reconfigurable according to two compilemtime constants： set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.展开更多
Nowadays, there has been a rapid increase in the variety and popularity of messaging systems and social networks. It is imperative to consider the effect and impact of the number of words feature on the verification p...Nowadays, there has been a rapid increase in the variety and popularity of messaging systems and social networks. It is imperative to consider the effect and impact of the number of words feature on the verification process for modern messaging systems such as Twitter, Facebook, SMS and Email. Given the volume of text is often a restricted factor (due to the nature of messaging systems), key to this investigation is a better understanding of what length of message is required to improve performance. A large historical dataset containing 50 participants, the four datasets containing a large number of messaging system samples (4539 samples for Facebook, 13,616 for Twitter, 6538 for Email and 106,359 for Text message), the best performance was for Text messages, with an EER of 7.6% if the number of words was more than nine;followed by Email with an EER of 14.9% if the number of words was between 25 to 60;then, Twitter tweets, with an EER of 22.5% if the number of words was less than ten. Finally, the Facebook platform with an EER of 31.9% if the number of words was over 11.展开更多
This paper delves into the baseline design under the baseline parameterization model in experimental design, focusing on the relationship between the K-aberration criterion and the word length pattern (WLP) of regular...This paper delves into the baseline design under the baseline parameterization model in experimental design, focusing on the relationship between the K-aberration criterion and the word length pattern (WLP) of regular two-level designs. The paper provides a detailed analysis of the relationship between K5and the WLP for regular two-level designs with resolution t=3, and proposes corresponding theoretical results. These results not only theoretically reveal the connection between the orthogonal parameterization model and the baseline parameterization model but also provide theoretical support for finding the K-aberration optimal regular two-level baseline designs. It demonstrates how to apply these theories to evaluate and select the optimal experimental designs. In practical applications, experimental designers can utilize the theoretical results of this paper to quickly assess and select regular two-level baseline designs with minimal K-aberration by analyzing the WLP of the experimental design. This allows for the identification of key factors that significantly affect the experimental outcomes without frequently changing the factor levels, thereby maximizing the benefits of the experiment.展开更多
基金the National Nature Science Foundation of China (60774021)
文摘This article deals with two important issues in digital filter implementation： roundoff noise and limit cycles. A novel class of robust state-space realizations, called normal realizations, is derived and characterized. It is seen that these realizations are free of limit cycles. Another interesting property of the normal realizations is that they yield a minimal error propagation gain. The optimal realization problem, defined as to find those normal realizations that minimize roundoff noise gain, is formulated and solved analytically. A design example is presented to demonstrate the behavior of the optimal normal realizations and to compare them with several well-known digital filter realizations in terms of minimizing the roundoff noise and the error propagation.
基金Supported by the National Natural Science Foundation of China(60972018)
文摘The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system performance,a modified scheme is presented to decline the resource consumption without too much degradation on the signal to noise ratio（SNR）.Theoretical analysis and numerical results demonstrate that compared to the traditional design,the proposed scheme could save dozens of memory resources.The scheme also includes some selectable parameters to achieve desired performance in various circumstances.Different from previous work in DDCs that concentrates mostly on the structure design,this paper considers special applications such as ultra-low symbol rate receivers.
基金Supported by the Funds for Creative Research Groups of China 60521003）, the State Key Program of National Natural Science of ina （60534010）, National Natural Science Foundation of China （60674021）, the Funds of Ph.D. Program of Ministry of Eduction, China （20060145019）, and the 111 Project （B08015）
文摘过滤有限的词长度(FWL ) 为线性分离时间的系统影响的问题的 nonfragile H 在这份报纸被调查。要设计的过滤器被假定与添加剂获得变化，它在过滤器实现上反映 FWL 效果。结构化的顶点隔板的一个观点被建议处理这个问题并且利用了以一套线性矩阵不平等(LMI ) 为 nonfragile H 过滤器设计开发足够的条件。设计使扩充系统变为 asymptotically 稳定并且保证 H 变细水平不到规定水平。一个数字例子被给说明建议方法的效果。
文摘The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.
文摘ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms： Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer4evel （RTL） level as technology-independent reusable IP-cores. They are reconfigurable according to two compilemtime constants： set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.
文摘Nowadays, there has been a rapid increase in the variety and popularity of messaging systems and social networks. It is imperative to consider the effect and impact of the number of words feature on the verification process for modern messaging systems such as Twitter, Facebook, SMS and Email. Given the volume of text is often a restricted factor (due to the nature of messaging systems), key to this investigation is a better understanding of what length of message is required to improve performance. A large historical dataset containing 50 participants, the four datasets containing a large number of messaging system samples (4539 samples for Facebook, 13,616 for Twitter, 6538 for Email and 106,359 for Text message), the best performance was for Text messages, with an EER of 7.6% if the number of words was more than nine;followed by Email with an EER of 14.9% if the number of words was between 25 to 60;then, Twitter tweets, with an EER of 22.5% if the number of words was less than ten. Finally, the Facebook platform with an EER of 31.9% if the number of words was over 11.
文摘This paper delves into the baseline design under the baseline parameterization model in experimental design, focusing on the relationship between the K-aberration criterion and the word length pattern (WLP) of regular two-level designs. The paper provides a detailed analysis of the relationship between K5and the WLP for regular two-level designs with resolution t=3, and proposes corresponding theoretical results. These results not only theoretically reveal the connection between the orthogonal parameterization model and the baseline parameterization model but also provide theoretical support for finding the K-aberration optimal regular two-level baseline designs. It demonstrates how to apply these theories to evaluate and select the optimal experimental designs. In practical applications, experimental designers can utilize the theoretical results of this paper to quickly assess and select regular two-level baseline designs with minimal K-aberration by analyzing the WLP of the experimental design. This allows for the identification of key factors that significantly affect the experimental outcomes without frequently changing the factor levels, thereby maximizing the benefits of the experiment.
