To obtain a better placement result, a partitioning-based placement algorithm with wirelength prediction called HJ-Pl is presented. A new method is proposed to estimate proximity of interconnects in a netlist, which i...To obtain a better placement result, a partitioning-based placement algorithm with wirelength prediction called HJ-Pl is presented. A new method is proposed to estimate proximity of interconnects in a netlist, which is capable of predicting not only short interconnects but long interconnects accurately. The predicted wirelength is embedded into the partitioning tool of bisection-based global placement, which can guide our placement towards a solution with shorter interconnects. In addition, the timing objective can be handled within the algorithm by minimizing the critical path delay. Experimental results show that, compared to Capol0. 5, mPL6, and NTUplace, HJ-P1 outperforms these placers in terms of wirelength and run time. The improvements in terms of average wirelength over Capo10. 5, mPL6 and NPUplace are 13%, 3%, and 9% with only 19%, 91%, and 99% of their runtime, respectively. By integrating the predicted wirelength-driven clustering into Capo10. 5, the placer is able to reduce average wirelength by 3%. The timing-driven HJ-P1 can reduce the critical path delay by 23%.展开更多
We study embeddings of the n-dimensional hypercube into the circuit with 2nvertices.We prove that the circular wirelength attains a minimum by gray coding;that was called the CT conjecture by Chavez and Trapp(Discrete...We study embeddings of the n-dimensional hypercube into the circuit with 2nvertices.We prove that the circular wirelength attains a minimum by gray coding;that was called the CT conjecture by Chavez and Trapp(Discrete Applied Mathematics,1998).This problem had claimed to be settled by Ching-Jung Guu in her doctoral dissertation“The circular wirelength problem for hypercubes”(University of California,Riverside,1997).Many argue there are gaps in her proof.We eliminate the gaps in her dissertation.展开更多
Standard cell placement algorithms have been at the forefront of academic research concerning the physical design stages of VLSI design flows. The penultimate step of a standard cell placement procedure is legalizatio...Standard cell placement algorithms have been at the forefront of academic research concerning the physical design stages of VLSI design flows. The penultimate step of a standard cell placement procedure is legalization. In this step the manufacturability of the design is directly settled, and the quality of the solution, in terms of wirelength, congestion, timing and power consumption is indirectly defined. Since the heavy lifting regarding processing is performed by global placers, fast legalization solutions are protruded in state-of-the-art design flows. In this paper we propose and evaluate a legalization scheme that surpasses in execution speed two of the most widely used legalizers, without not only corrupting the quality of the final solution in terms of interconnection wirelength but improving it in the process.展开更多
基金The National Key Project of Scientific and Technical Supporting Programs (No.2006BAK07B04)
文摘To obtain a better placement result, a partitioning-based placement algorithm with wirelength prediction called HJ-Pl is presented. A new method is proposed to estimate proximity of interconnects in a netlist, which is capable of predicting not only short interconnects but long interconnects accurately. The predicted wirelength is embedded into the partitioning tool of bisection-based global placement, which can guide our placement towards a solution with shorter interconnects. In addition, the timing objective can be handled within the algorithm by minimizing the critical path delay. Experimental results show that, compared to Capol0. 5, mPL6, and NTUplace, HJ-P1 outperforms these placers in terms of wirelength and run time. The improvements in terms of average wirelength over Capo10. 5, mPL6 and NPUplace are 13%, 3%, and 9% with only 19%, 91%, and 99% of their runtime, respectively. By integrating the predicted wirelength-driven clustering into Capo10. 5, the placer is able to reduce average wirelength by 3%. The timing-driven HJ-P1 can reduce the critical path delay by 23%.
文摘We study embeddings of the n-dimensional hypercube into the circuit with 2nvertices.We prove that the circular wirelength attains a minimum by gray coding;that was called the CT conjecture by Chavez and Trapp(Discrete Applied Mathematics,1998).This problem had claimed to be settled by Ching-Jung Guu in her doctoral dissertation“The circular wirelength problem for hypercubes”(University of California,Riverside,1997).Many argue there are gaps in her proof.We eliminate the gaps in her dissertation.
文摘Standard cell placement algorithms have been at the forefront of academic research concerning the physical design stages of VLSI design flows. The penultimate step of a standard cell placement procedure is legalization. In this step the manufacturability of the design is directly settled, and the quality of the solution, in terms of wirelength, congestion, timing and power consumption is indirectly defined. Since the heavy lifting regarding processing is performed by global placers, fast legalization solutions are protruded in state-of-the-art design flows. In this paper we propose and evaluate a legalization scheme that surpasses in execution speed two of the most widely used legalizers, without not only corrupting the quality of the final solution in terms of interconnection wirelength but improving it in the process.
