This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability o...This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.展开更多
An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line volt...An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is chosen in order to make the access transistor operate in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The WNM shift amount is determined from the measured WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. Together with the maximum likelihood method, a normal distribution of the AWNM drastically improves development efficiency because the write failure probability can be estimated from a small number of samples. The effectiveness of the proposed method is verified using the Monte Carlo simulation.展开更多
随着工艺技术的缩减,功耗问题日益严重,低功耗优化技术成了当前研究的一大重点.对处理器的功耗优化可以从设计过程、运行过程和空闲状态来考虑.本文重点研究了处理器在运行时的功率管理技术,即动态功率管理技术.它主要包括动态电压缩减D...随着工艺技术的缩减,功耗问题日益严重,低功耗优化技术成了当前研究的一大重点.对处理器的功耗优化可以从设计过程、运行过程和空闲状态来考虑.本文重点研究了处理器在运行时的功率管理技术,即动态功率管理技术.它主要包括动态电压缩减DVS(Dynamic Voltage Scaling)和动态阈值电压缩减DVTS(Dynamic VTH Scaling)的方法,其中DVTS又是通过对衬底偏压的调整来实现阈值电压的调制的.本文重点研究了这两种技术的原理和实现结构,并分析了它们目前的研究和应用。展开更多
基金supported by the Grant number 600/1792 from the vice presidency of research and technology of Shahid Beheshti University,G.C
文摘This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.
文摘An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is chosen in order to make the access transistor operate in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The WNM shift amount is determined from the measured WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. Together with the maximum likelihood method, a normal distribution of the AWNM drastically improves development efficiency because the write failure probability can be estimated from a small number of samples. The effectiveness of the proposed method is verified using the Monte Carlo simulation.
文摘随着工艺技术的缩减,功耗问题日益严重,低功耗优化技术成了当前研究的一大重点.对处理器的功耗优化可以从设计过程、运行过程和空闲状态来考虑.本文重点研究了处理器在运行时的功率管理技术,即动态功率管理技术.它主要包括动态电压缩减DVS(Dynamic Voltage Scaling)和动态阈值电压缩减DVTS(Dynamic VTH Scaling)的方法,其中DVTS又是通过对衬底偏压的调整来实现阈值电压的调制的.本文重点研究了这两种技术的原理和实现结构,并分析了它们目前的研究和应用。
