It is highly attractive to develop an efficient and flexible large eddy simulation(LES)technique for high-Reynolds-number atmospheric boundary layer(ABL)simulation using the low-order numerical scheme on a relatively ...It is highly attractive to develop an efficient and flexible large eddy simulation(LES)technique for high-Reynolds-number atmospheric boundary layer(ABL)simulation using the low-order numerical scheme on a relatively coarse grid,that could reproduce the logarithmic profile of the mean velocity and some key features of large-scale coherent structures in the outer layer.In this study,an improved near-wall correction scheme for the vertical gradient of the resolved streamwise velocity in the strain-rate tensor is proposed to calculate the eddy viscosity coefficient in the subgrid-scale(SGS)model.The LES code is realized with a second-order finite-difference scheme,the scale-dependent dynamic SGS stress model,the equilibrium wall stress model,and the proposed correction scheme.Very-high-Reynolds-number ABL flow simulation under the neutral stratification condition is conducted to assess the performance of the method in predicting the mean and fluctuating characteristics of the rough-wall turbulence.It is found that the logarithmic profile of the mean streamwise velocity and some key features of large-scale coherent structures can be reasonably predicted by adopting the proposed correction method and the low-order numerical scheme.展开更多
A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a ...A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling ap- plications and also verified by many widely acknowledged image quality measures. The reconfigu- rable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array （FPGA） devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework.展开更多
Carbon nanotube field-effect transistors(CNTFETs)are increasingly recognized as a viable option for creating high-performance,low-power,and densely integrated circuits(ICs).Advancements in carbon-based electronics,enc...Carbon nanotube field-effect transistors(CNTFETs)are increasingly recognized as a viable option for creating high-performance,low-power,and densely integrated circuits(ICs).Advancements in carbon-based electronics,encompassing materials and device technology,have enabled the fabrication of circuits with over 1000 gates,marking carbon-based integrated circuit design as a burgeoning field of research.A critical challenge in the realm of carbon-based very-large-scale integration(VLSI)is the lack of suitable automated design methodologies and infrastructure platforms.In this study,we present the development of a waferscale 3μm carbon-based complementary metal-oxide-semiconductor(CMOS)process design kit(PDK)(3μm-CNTFETs-PDK)compatible with silicon-based Electronic Design Automation(EDA)tools and VLSI circuit design flow.The proposed 3μm-CNTFETs-PDK features a contacted gate pitch(CGP)of 21μm,a gate density of 128 gates/mm^(2),and a transistor density of 554 transistors/mm^(2),with an intrinsic gate delay around 134 ns.Validation of the 3μm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits.Leveraging the carbon-based PDK and a silicon-based design platform,we successfully implemented a complete 64-bit static random-access memory(SRAM)circuit system for the first time,which exhibited timing,power,and area characteristics of clock@10 kHz,122.1μW,3795μm×2810μm.This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow,thereby laying the groundwork for future carbon-based VLSI advancements.展开更多
基金supported by the National Natural Science Foundation of China (Grant No.92052202)the Fundamental Research Funds for the Central Universities (Grant No.lzujbky-2021-ey19).
基金Project supported by the National Natural Science Foundation of China(No.11490551)the Fundamental Research Funds for the Central Universities(Nos.lzujbky-2016-k13 and lzujbky-2018-k07)
文摘It is highly attractive to develop an efficient and flexible large eddy simulation(LES)technique for high-Reynolds-number atmospheric boundary layer(ABL)simulation using the low-order numerical scheme on a relatively coarse grid,that could reproduce the logarithmic profile of the mean velocity and some key features of large-scale coherent structures in the outer layer.In this study,an improved near-wall correction scheme for the vertical gradient of the resolved streamwise velocity in the strain-rate tensor is proposed to calculate the eddy viscosity coefficient in the subgrid-scale(SGS)model.The LES code is realized with a second-order finite-difference scheme,the scale-dependent dynamic SGS stress model,the equilibrium wall stress model,and the proposed correction scheme.Very-high-Reynolds-number ABL flow simulation under the neutral stratification condition is conducted to assess the performance of the method in predicting the mean and fluctuating characteristics of the rough-wall turbulence.It is found that the logarithmic profile of the mean streamwise velocity and some key features of large-scale coherent structures can be reasonably predicted by adopting the proposed correction method and the low-order numerical scheme.
基金Supported by the National Natural Science Foundation of China(No.60972126)the Joint Funds of the National Natural Science Foundation of China(No.U0935002/L05)+1 种基金the Beijing Municipal Natural Science Foundation(No.4102060)the State Key Program of the National Natural Science of China(No.61032007)
文摘A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling ap- plications and also verified by many widely acknowledged image quality measures. The reconfigu- rable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array （FPGA） devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework.
基金The authors gratefully acknowledge fundings from the Strategic Priority Research Program of Chinese Academy of Sciences(CAS)(No.XDA0330401)CAS Youth Interdisciplinary Team(No.JCTD-2022-07).
文摘Carbon nanotube field-effect transistors(CNTFETs)are increasingly recognized as a viable option for creating high-performance,low-power,and densely integrated circuits(ICs).Advancements in carbon-based electronics,encompassing materials and device technology,have enabled the fabrication of circuits with over 1000 gates,marking carbon-based integrated circuit design as a burgeoning field of research.A critical challenge in the realm of carbon-based very-large-scale integration(VLSI)is the lack of suitable automated design methodologies and infrastructure platforms.In this study,we present the development of a waferscale 3μm carbon-based complementary metal-oxide-semiconductor(CMOS)process design kit(PDK)(3μm-CNTFETs-PDK)compatible with silicon-based Electronic Design Automation(EDA)tools and VLSI circuit design flow.The proposed 3μm-CNTFETs-PDK features a contacted gate pitch(CGP)of 21μm,a gate density of 128 gates/mm^(2),and a transistor density of 554 transistors/mm^(2),with an intrinsic gate delay around 134 ns.Validation of the 3μm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits.Leveraging the carbon-based PDK and a silicon-based design platform,we successfully implemented a complete 64-bit static random-access memory(SRAM)circuit system for the first time,which exhibited timing,power,and area characteristics of clock@10 kHz,122.1μW,3795μm×2810μm.This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow,thereby laying the groundwork for future carbon-based VLSI advancements.
