The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic ...The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.展开更多
基金supported by the Shenzhen Government R&D Project under Grant No.JC200903160361A
文摘The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.
