This survey traces the evolution of Simulated Annealing(SA)based algorithms for Very Large Scale Integration(VLSI)floorplanning and placement.It begins with the foundational TimberWolf package,which established SA as ...This survey traces the evolution of Simulated Annealing(SA)based algorithms for Very Large Scale Integration(VLSI)floorplanning and placement.It begins with the foundational TimberWolf package,which established SA as a state-ofthe-art method.It then examines two distinct paths of improvement that address the limitations of the original approach.The first path focuses on achieving scalability and routability for modern,large-scale designs by integrating a multilevel framework and direct congestion modeling.The second path re-engineers the core optimization engine itself,introducing a novel three-stage annealing schedule for faster convergence while handling complex geometric constraints.展开更多
In this paper,a K-line location algorithm for building block cells in LSI/VLSI ispresented.When the relative positions of rectangular cells are given,there are 2 states accordingto the two orientations of a cell.It is...In this paper,a K-line location algorithm for building block cells in LSI/VLSI ispresented.When the relative positions of rectangular cells are given,there are 2 states accordingto the two orientations of a cell.It is proved that to find the optimum solution from the 2~N statescan be reduced to calculate the N states in K-line algorithm.So the algorithm is shown veryeffective and can be used with association for cluster method in BBL placement.Under certainconditions,this method can also be used to pesudo BBL placement directly.展开更多
文摘This survey traces the evolution of Simulated Annealing(SA)based algorithms for Very Large Scale Integration(VLSI)floorplanning and placement.It begins with the foundational TimberWolf package,which established SA as a state-ofthe-art method.It then examines two distinct paths of improvement that address the limitations of the original approach.The first path focuses on achieving scalability and routability for modern,large-scale designs by integrating a multilevel framework and direct congestion modeling.The second path re-engineers the core optimization engine itself,introducing a novel three-stage annealing schedule for faster convergence while handling complex geometric constraints.
文摘In this paper,a K-line location algorithm for building block cells in LSI/VLSI ispresented.When the relative positions of rectangular cells are given,there are 2 states accordingto the two orientations of a cell.It is proved that to find the optimum solution from the 2~N statescan be reduced to calculate the N states in K-line algorithm.So the algorithm is shown veryeffective and can be used with association for cluster method in BBL placement.Under certainconditions,this method can also be used to pesudo BBL placement directly.
