This paper proposes a technique that uses the number of oscillation cycles(NOC)of a VCO-based comparator to set multiple adaptive bypass windows in a 12-bit successive approximation register(SAR)analog-to-digital conv...This paper proposes a technique that uses the number of oscillation cycles(NOC)of a VCO-based comparator to set multiple adaptive bypass windows in a 12-bit successive approximation register(SAR)analog-to-digital converter(ADC).The analysis of the number of bit cycles,power and static performance shows that three adaptive bypass windows reduce power consumption,and decrease DNL and have similar INL,compared with the SAR ADC without bypass windows.In addition,a 1-bit split-and-recombination redundancy technique and a general bypass logic digital error correction method are proposed to address the settling issues and optimize the size of the bypass window.This design is implemented in 40 nm CMOS technology.The conversion frequency of the ADC reaches up to 30 MS/s.The ADC achieves an SFDR of 85.35 dB and 11.12-bit ENOB with Nyquist input,consuming 380μW,down from 427μW without multiple adaptive bypass windows,at a 1.1 V supply,resulting in a figure of merit(FoM)of 5.69 fJ/conversion-step.展开更多
The benefits of technology scaling have fueled interest in realizing time-domain oversampling(?∑) of Analog-to-Digital Converters(ADCs). Voltage-Controlled Oscillators(VCO) are increasingly used to design ?∑ADCs bec...The benefits of technology scaling have fueled interest in realizing time-domain oversampling(?∑) of Analog-to-Digital Converters(ADCs). Voltage-Controlled Oscillators(VCO) are increasingly used to design ?∑ADCs because of their simplicity, high digitization, and low-voltage tolerance, making them a promising candidate to replace the classical Operational Transconductance Amplifier(OTA) in ?∑ ADC design. This work aims to provide a summary of the fully VCO-based ?∑ ADCs that are highly digital and scaling-friendly. This work presents a review of first-order and high-order VCO-based ?∑ ADCs with several techniques and architectures to mitigate the nonidealities introduced by VCO, achieving outstanding power efficiency. The contributions and drawbacks of these techniques and architectures are also discussed.展开更多
基金supported by the National Natural Science Foundation of China under Grant 61534002 and Grant 61761136015.
文摘This paper proposes a technique that uses the number of oscillation cycles(NOC)of a VCO-based comparator to set multiple adaptive bypass windows in a 12-bit successive approximation register(SAR)analog-to-digital converter(ADC).The analysis of the number of bit cycles,power and static performance shows that three adaptive bypass windows reduce power consumption,and decrease DNL and have similar INL,compared with the SAR ADC without bypass windows.In addition,a 1-bit split-and-recombination redundancy technique and a general bypass logic digital error correction method are proposed to address the settling issues and optimize the size of the bypass window.This design is implemented in 40 nm CMOS technology.The conversion frequency of the ADC reaches up to 30 MS/s.The ADC achieves an SFDR of 85.35 dB and 11.12-bit ENOB with Nyquist input,consuming 380μW,down from 427μW without multiple adaptive bypass windows,at a 1.1 V supply,resulting in a figure of merit(FoM)of 5.69 fJ/conversion-step.
基金This work was supported by the National Natural Science Foundation of China (Nos. 61934009 and 62090042)Beijing National Research Center for Information Science and Technology, Beijing Innovation Center for Future Chips (ICFC)the Academician Expert Open Fund of Beijing Smart-chip Microelectronics Technology Co., Ltd.
文摘The benefits of technology scaling have fueled interest in realizing time-domain oversampling(?∑) of Analog-to-Digital Converters(ADCs). Voltage-Controlled Oscillators(VCO) are increasingly used to design ?∑ADCs because of their simplicity, high digitization, and low-voltage tolerance, making them a promising candidate to replace the classical Operational Transconductance Amplifier(OTA) in ?∑ ADC design. This work aims to provide a summary of the fully VCO-based ?∑ ADCs that are highly digital and scaling-friendly. This work presents a review of first-order and high-order VCO-based ?∑ ADCs with several techniques and architectures to mitigate the nonidealities introduced by VCO, achieving outstanding power efficiency. The contributions and drawbacks of these techniques and architectures are also discussed.
