A full on-chip CMOS low-dropout（LDO） voltage regulator with high PSR is presented.Instead of relying on the zero generated by the load capacitor and its equivalent series resistance,the proposed LDO generates a zero...A full on-chip CMOS low-dropout（LDO） voltage regulator with high PSR is presented.Instead of relying on the zero generated by the load capacitor and its equivalent series resistance,the proposed LDO generates a zero by voltage-controlled current sources for stability.The compensating capacitor for the proposed scheme is only 0.18 pF,which is much smaller than the capacitor of the conventional compensation scheme.The full on-chip LDO was fabricated in commercial 0.35μm CMOS technology.The active chip area of the LDO（including the bandgap voltage reference） is 400×270μm^2.Experimental results show that the PSR of the LDO is-58.7 dB at a frequency of 10 Hz and-20 dB at a frequency of 1 MHz.The proposed LDO is capable of sourcing an output current up to 50 mA.展开更多
A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real ...A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR （equivalent series resistance） of the output capacitor. The unit gain frequency of the LDO loop can achieve 1.5 MHz, improving the transient response. The PSR of the LDO is larger than 45 dB within 0-40 kHz. The static current of the LDO at heavy load of 100 mA is 57 μA and the dropout voltage of the LDO is 150 mV. Experimental results show that a setting time of 10 ks is achieved, and the variation of output voltage is smaller than 35 mV for a 100 mA load step in transient response of the LDO.展开更多
基金Project supported by the National Science and Technology Major Project,China(No.2009ZX03007-002).
文摘A full on-chip CMOS low-dropout（LDO） voltage regulator with high PSR is presented.Instead of relying on the zero generated by the load capacitor and its equivalent series resistance,the proposed LDO generates a zero by voltage-controlled current sources for stability.The compensating capacitor for the proposed scheme is only 0.18 pF,which is much smaller than the capacitor of the conventional compensation scheme.The full on-chip LDO was fabricated in commercial 0.35μm CMOS technology.The active chip area of the LDO（including the bandgap voltage reference） is 400×270μm^2.Experimental results show that the PSR of the LDO is-58.7 dB at a frequency of 10 Hz and-20 dB at a frequency of 1 MHz.The proposed LDO is capable of sourcing an output current up to 50 mA.
基金supported by State Key Laboratory of ASIC and Systems of Fudan University and NSF(No.61076027)
文摘A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR （equivalent series resistance） of the output capacitor. The unit gain frequency of the LDO loop can achieve 1.5 MHz, improving the transient response. The PSR of the LDO is larger than 45 dB within 0-40 kHz. The static current of the LDO at heavy load of 100 mA is 57 μA and the dropout voltage of the LDO is 150 mV. Experimental results show that a setting time of 10 ks is achieved, and the variation of output voltage is smaller than 35 mV for a 100 mA load step in transient response of the LDO.
